Cadence – Redefining EDA Through Computational Software

Cadence – Redefining EDA Through Computational Software
by Mike Gianfagna on 05-12-2020 at 10:00 am

Screen Shot 2020 05 09 at 6.52.49 PM

Based on what I’m seeing, I believe Cadence is looking at the world a bit differently these days. I first reported about their approach to machine learning for EDA in March, and then there was their white paper about Intelligent System Design in April. It’s now May, and Cadence is shaking things up again with a new white paper entitled… Read More


Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
by Mike Gianfagna on 03-23-2020 at 6:00 am

FINAL2 Digital FF iSpatial Flow hi res

Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More


Machine Learning for EDA – Inside, Outside and Everywhere Else

Machine Learning for EDA – Inside, Outside and Everywhere Else
by Mike Gianfagna on 03-18-2020 at 6:00 am

Paul Cunningham

Artificial intelligence (AI) is everywhere. The rise of the machines is upon us in case you haven’t noticed. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making breakfast. We hear a lot about the macro, end-product impact of this technology, but there… Read More


Webinar – FPGA Native Block Floating Point for Optimizing AI/ML Workloads

Webinar – FPGA Native Block Floating Point for Optimizing AI/ML Workloads
by Tom Simon on 02-25-2020 at 10:00 am

block float example

Block floating point (BFP) has been around for a while but is just now starting to be seen as a very useful technique for performing machine learning operations. It’s worth pointing out up front that bfloat is not the same thing. BFP combines the efficiency of fixed point operations and also offers the dynamic range of full floating… Read More


Cadence Dives Deeper at Linley Fall Processor Conference

Cadence Dives Deeper at Linley Fall Processor Conference
by Randy Smith on 11-05-2019 at 10:00 am

I wrote about Cadence AI IP not long ago when I covered the Cadence Automotive Summit at the end of July (Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving, Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear). One of those two blogs remains one of my most widely … Read More


BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA

BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA
by Tom Simon on 10-31-2019 at 6:00 am

Back in May I wrote an article on the new Speedster7t from Achronix. This chip brings together Network on Chip (NoC) interconnect, high speed Ethernet and memory connections, and processing elements optimized for AI/ML. Speedster7t is a very exciting new FPGA that can be used effectively to accelerate a wide range of processing… Read More


DAC 2020 – Call for Contributions

DAC 2020 – Call for Contributions
by Daniel Payne on 10-28-2019 at 6:00 am

57DAC in SFO

My first DAC was in 1987 so I’ve seen our industry expand greatly over the years, and I expect that #57DAC on July 19-23, 2020 in SFO to be another exciting event to attend for semiconductor professionals from around the globe. What makes DAC so compelling for me to visit are the people, exhibitors, panel discussions, technical… Read More


GLOBALFOUNDRIES and Arm Showcase Broad Range of Partnership

GLOBALFOUNDRIES and Arm Showcase Broad Range of Partnership
by Randy Smith on 10-21-2019 at 10:00 am

I previously blogged on the GLOBALFOUNDRIES (GF) Technology Conference (GTC) held in Santa Clara, CA. The main takeaway that I shared in that blog was that GF’s announced “pivot” to a specialty foundry announced over a year ago, including its decision not to pursue 7nm and smaller nodes, appears to be working and GF is gaining momentum.… Read More


Webinar – AI/ML SoC Memory and Interconnect IP Perspectives

Webinar – AI/ML SoC Memory and Interconnect IP Perspectives
by Tom Simon on 10-08-2019 at 10:00 am

For decades development work on Artificial Intelligence (AI) and Machine Learning (ML) was done on traditional CPUs and memory configurations. Now that we are in the “hockey stick” upturn in deployment of AI and ML, the search is on for the most efficient types of processing architectures. The result is a wave of development for… Read More


The GF Pivot, Specialization Defined

The GF Pivot, Specialization Defined
by Randy Smith on 10-04-2019 at 6:00 am

On August 27, 2018, GLOBALFOUNDRIES (GF) announced that they were no longer going to compete in the race to the next smaller semiconductor node, at that time, the 7nm node. While surprising to some, on further analysis this move made sense. TSMC had announced its plan to invest around $25B in the 5nm technology node. GF revenue is … Read More