Can I ask you a personal question dear reader? It is only fair, you know so much about me and all, so here goes… Why are you still hand coding you’re FPGA design? Surely you are not hand coding interfaces, like PCie, SRIO, DDR, GbE, JESD204B, HMC etc… Correct? OK, why then are you still hand coding the guts of the world’s best, super-duper… Read More
Tag: 20nm
I’d give my right ARM to be ambidextrous
Baseball loves a good switch hitter – from Frisch to Mantle to Rose to Murray to Jones, they are a rare and valuable commodity. AMD is calling on ambidexterity for its processors in 2015 and beyond, this week tipping plans for 20nm “Project SkyBridge” parts in either ARM or X86 with a common footprint. What remains to be seen is where… Read More
TSMC Updates: 20nm, 16nm, and 10nm!
*Spoiler Alert: The Sky is Not Falling*
The TSMC Technology Symposium last month provided a much needed technology refresh to counter aging industry experts (they make their living selling reports) who have been somewhat negative on the future of the fabless semiconductor ecosystem. If the sky wasn’t falling who would… Read More
FD-SOI Not Just For France Any More, China Signs On?
The COO of ST Microelectronics, Jean-Marc Chery announced that they have signed a new foundry agreement for FD-SOI. What he actually said doesn’t reveal who the foundry in question is:“We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assures… Read More
Xilinx Quarterly Results: 20nm Prototypes
Xilinx announced their quarterly results last week. Because of their financial year not being aligned with their calendar year this is actually 4th quarter of their 2014 financial year. New Year’s Eve 2015 comes early for Xilinx. The results were very good. As Moshe Gavrielov, the CEO, said on the conference call:Xilinx… Read More
Handel Jones on FD-SOI vs FinFET
Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis… Read More
Xilinx’s UltraScale vs Arria 10 – Non dolet, Paete
The DSP48E2 (I do not come up with these names… Could have named it a multiplier thingy) in the Xilinx 20nm UltraScale family (I do not come up with these names… Could of named it Virtex-8, or Luke-8) is simply amazing. Today was good, as I began playing with UltraScale tools and seeing how the DSP checks out. I also encourage you to check… Read More
Getting an MPW Quote on My iPhone
As I blogged about recently, eSilicon have completely automated the quote process for their MPW shuttle service. You can use an online interface that runs in the browser but there is also an app that you can download from the App Store.
So I decided I had a few million dollars to burn and I’d get myself my very own TSMC 20nm parts.… Read More
Handel Jones Predicts Process Roadmap Slips
At the SEMI ISS conference earlier this week, the last speaker in the technology challenges section was Handel Jones of IBS. I’ve known Handel since the mid-1980s when he came to VLSI Technology and told us we were losing money on 90% of the designs we were doing but our cost model was not good enough and so we didn’t even… Read More
New Frontiers in Scan Diagnosis
As we move down into more and more advanced process nodes, the rules of how we test designs are having to change. One big challenge is the requirement to zoom in and fix problems by doing root cause analysis on test data alone, along with the rest of the design data such as detailed layout, optical proximity correction and so on. But without… Read More