Sign Off Design Challenges at Cutting Edge Technologies

As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips, an Arrow company, has developed innovative techniques for reaching design closure at these advanced nodes. They articulate what they have learned and how they apply specific techniques in an article titled “Sign Off the Chip (ASIC) Design Challenges and Solutions at Cutting Edge Technology” on their website, along with a case study available for download. Their goal is to tapeout customer ASIC designs on time with high yield and performance.

They cite disruptive megatrends such as IoT, Cloud, and 4G/5G networks, which impinge on a huge range of products such as entertainment, security, medical, wearables, automotive, and much more. These all need silicon that is produced on the most advanced process nodes. We see that in these applications there are stringent requirements for high frequency and/or low power operation. Each step of the design process from partitioning, geometry usage, routing/resource distribution, and block execution all play a role in silicon success.

The einfochips article focuses on three areas they see as central to SoC design, power planning, IR/EM, timing & physical design verification. Strictly speaking the quality of power planning affects IR/EM but is treated separately because there is more to power planning. In the latest process nodes, the design becomes denser and has more metal layers. Operating voltages are also typically lower, so there is less margin for error. To help here, einfochips takes advantage of intermediate layers for fortifying supply lines. Rather than dropping vias from top to bottom, they use lower metal to avoid creating blockages and distribute power more effectively. They also use power grid via reinforcement to gain up to 3-5 mV according to their article.

The two sources of IR drop are static and dynamic. It used to be that adding decoupling caps was sufficient for achieving IR drop sign off. To make additional gains, einfochips has developed a specialized method of IR drop aware placement. This is critical for buffer and inverter placement in routing channels.

Timing and PDV present their own challenges. The einfochips article discusses an example case where they had 360 setup violation and 20 hold violations. To close these violations, they relied on cell sizing and Vt swapping. They avoided buffer insertion due to the adverse effect on routing and area. Clocks of course were marked don’t touch and were addressed separately. They used their ECO flow to reach timing closure. This flow is described in some detail in their article.

In addition to the above challenges, other things like testing and packaging have to be addressed to produce a fully complete ASIC design. The article touches on the topic of test, highlighting reduced pin-count test as a way to improve test and make use of testers with pin limitations. This method can support at-speed test and maximizes fault coverage. They also include a description of packaging challenges for nanometer chips and new advanced multi-die packages.

The article does a good job of summarizing the design challenges in ASIC sign-off at advanced nodes. It includes details of their flow and also has a link to a case study that has more specifics. If you are looking to build an ASIC for any application that requires advanced process nodes, this article may prove very interesting. The article is available on the einfochips website.

eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.

For more information connect with eInfochips today.

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