As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More
Monday morning at DAC I met with Real Intent to get an update on their SoC sign-off tools:
- Dr. Prakash Narain, President and CEO
- Graham Bell, Sr. Dir. Mktg.
Years ago Prakash was at IBM the only two years that they attended DAC, in an attempt to offer their internal EDA tools to the EDA marketplace. Graham worked at Nassda marketing the… Read More