Webinar: Find More Bugs, Hit the Most Difficult Scenarios Faster

Webinar: Find More Bugs, Hit the Most Difficult Scenarios Faster
by Admin on 12-20-2022 at 12:51 pm

Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.

Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles… Read More


Sign Off Design Challenges at Cutting Edge Technologies

Sign Off Design Challenges at Cutting Edge Technologies
by Tom Simon on 12-03-2020 at 6:00 am

Power and Ground Design Challenges

As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More