TSMC @ #54DAC!

TSMC has been an ardent supporter of DAC for the last 18 years which has brought in the other foundries because, as the industry leader, wherever TSMC goes the other foundries naturally follow. The exception of course is Intel Custom Foundry because they march to the beat of a different drummer, if you know what I mean. The CoFluent group of Intel does exhibit at DAC, yes Intel became an EDA company with the purchase of French ESL company CoFluent in 2011. I’m not sure who their customers are but probably not the growing number of companies that compete with Intel due to their acquisitions but I digress…

This year TSMC has some notable speakers that you may want to catch:

TECHNICAL PANEL
Minimizing IC Power Consumption: Top Down or Bottom up Design Methodology. What is the Starting Point?
Moderator – John Blyler – Electronic Design Mag.
Aditya Mukherjee – Microsoft
Tim Saxe – QuickLogic Corp.
Abhishek Ranjan – Mentor, A Siemens Business
Ronald Martino – NXP Semiconductors
Lluis Paris – TSMC
Jon Adams – ON Semiconductor

Lluis Paris is Director of World Wide IP Alliance at TSMC and a recognized IP expert, in fact he is the top IP person I know and that is saying a lot because I know many. Lluis came to TSMC from the Emerging Memory Technology acquisition where he was COO. Not only does Lluis have a PhD in Microelectronics, he also has an MBA so he is definitely worth your time. I also know Tim Saxe from my Zycad and GateField FPGA days. Tim has a PhD in Electrical Engineering from Stanford and is a straight shooter with YEARS and YEARS of experience so he is definitely worth listening to.

The panel is on Monday at 3:30pm in the Convention Center, Ballroom G and I will be at this one. Lluis is also participating in the Mentor Booth Panel on the Impact of ISO 26262 on the fabless ecosystem on Tuesday at 5pm.

Tom Quan is also one of my favorite TSMC presenters. Tom has been at TSMC for ten years and before that he was an EDA staple. Prior to EDA, he was a Design Engineer at Intel. Tom is an AMS expert so that is where you can usually find him. This year he is quite busy:

LUNCH PANELS
Cadence: High Performance Digital Design at 7nm
Tuesday 12:00pm at the Convention Center – Ballroom B & C

Synopsys: Custom Compiler in 7nm
Tuesday 11:30am Hilton Hotel, 6th Floor, Austin Grand Ballroom H

BOOTH PRESENTATIONS
Synopsys: Design Enablement for HPC, Mobile, IoT and Automotive Applications
Monday 2:00pm

Cadence: TSMC Automotive Design Enablement Platform
Tom Quan Tuesday 2:00pm, Chek-San Leong Tuesday at 4:00, and Captain Liu Wednesday 1:30pm.

Captain Liu spent his career in EDA (Springsoft/Synopsys) before coming to TSMC two years ago. Captain is also busy at DAC:

BOOTH PRESENTATIONS
Cadence: TSMC-Cadence Collaboration for Digital Design Enablement at 7nm Monday at 11:30am and 1pm.
Synopsys: Design Enablement for HPC, Mobile, IoT and Automotive Applications Tuesday at 1:30pm.
ANSYS: Tool Flow Verification Monday at 2:45pm.

My good friend Willy Chen will be on the Synopsys breakfast panel: ARM, Synopsys and TSMC collaboration to enable high performance design with the latest processors and FinFET processes, including 7nm Monday morning. I will be at that one as well.

Last but not least Libby Aston and Chek-San Leong will be presenting Design Enablement for HPC, Mobile, IoT and Automotive Applicationsat the Chip Estimate booth on Tuesday and Wednesday at 1:30pm respectively.

You can see all of the DAC events HERE.

Please notice that TSMC 7nm is all over DAC this year meaning that we will see production chips in 2018, absolutely! Exciting times, I hope to see you there!