Top 10 Updates from the TSMC Technology Symposium, Part I

Last week, TSMC held their 23rd annual technical symposium in Santa Clara. In the Fall, TSMC conducts the OIP updates from EDA/IP partners and customers. The theme of the Spring symposium is solely on TSMC’s technology development status and the future roadmap. Indirectly, the presentations also provide insight into the electronics industry as a whole, based upon the market segments where TSMC is focusing, with their R&D investments.

The day was packed with information — some areas are clearly making significant strides, but just missed making the cut for the top updates, such as:

• fab expansion plans in Taiwan and China, with a major emphasis on fab matching techniques
• manufacturing focus on improved statistical process control, and the D0 defect density takedown ramp
• investment in advanced MEMS sensors: improved piezoelectric diaphragm materials and sensitivity; advances in CMOS image pixel sensors
• added emphasis on CMOS RF device characterization and fabrication improvements to reduce flicker noise
• a next-gen Integrated Fan-Out (InFO) multi-chip packaging technology (including RF characterization), with additional InFO die and HBM memory stack options
• a next-gen CoWoS offering, with larger, multi-reticle package sizes

Here are the (very subjective) “Top 10” technical and business updates from the symposium.

(#10) “Making the grade”

The qualification of a process technology requires addressing the environmental extremes of the target application markets. The emergence of the automotive market for advanced SoC’s has introduced additional AEC-Q100 qualification and reliability targets, as illustrated below.

Design IP is no longer strictly targeted for “industrial” or “commercial” applications, but rather a finer set of environments. Specifically, TSMC is addressing the automotive market by focusing on Grade 1 and Grade 0 (engine compartment) process qualification, and the corresponding device model fitting to wider temperature ranges.

TSMC “Foundation IP” is also being qualification accordingly. For example, the 16FFC high-density (HD) bit-cell based SRAM array qualification data were shown, with minimal change in VCC_min after Grade 0/1 HTOL stress.

The schedule for all IP to achieve Grade 1 and Grade 0 qualification for 16FFC (2Q’17) and N7 (2018) was briefly reviewed.

(#9) Platform-based PDK releases

Last year, TSMC introduced a focus on process development for four specific application platforms: Mobile, High-Performance Computing, Automotive, and IoT.

The strategy for future PDK releases aligns with these platforms, as described in #10 above. Here is the process versus platform matrix that TSMC presented:

(#8) “The global semiconductor market is very healthy.”

TSMC was very upbeat about the semi market, as a prelude to the discussion on gigafab phase expansion: “The global GDP for 2016 was $80T, with a projected growth rate of 2% this year. The global semiconductor market was $350B, with a projected growth rate of 6%.”

And they provided an additional point of interest, that would suggest the entrepreneurial spirit of the SoC industry is also undaunted: “We have 450 customers, with one new customer per week.” (my emphasis added)

(#7) “How low can you go?”

TSMC has continued to work on reducing the minimum VDD for process nodes, as part of introducing the ULP variant. For example, VDD_nominal for the LP variant of N16 is 0.8V, and 0.55V for the ULP offering.

A new, unique characterization effort that TSMC highlighted will be to offer a “near Vt supply” technology PDK variant. With regards to the IoT platform, TSMC will be qualifying 40nm near_Vt models and Foundation IP in 1H’2017.

It will be interesting to see how IP providers describe their near_Vt development strategy at the OIP Symposium this Fall.

(#6) On-chip memories will never be the same.

The data storage architecture for current SoC’s requires greater capacity, and specifically for non-volatile arrays, more robust retention and reliability. TSMC will be transitioning embedded flash and embedded DRAM development to two new technology options:

• embedded Resistive RAM (ReRAM), for an eFlash replacement: 40nm in 2H’17
• embedded Magnetic RAM (MRAM), for eFlash and eDRAM, 28nm in 2H’18

TSMC did not go into detail, but I would assume the MRAM uses the spin-transfer torque (STT) write access methodology.

A subsequent article will cover the remaining top five updates from the symposium.

-chipguy

Also read: Top 10 Updates from the TSMC Technology Symposium, Part II