I’ve written before about the basic capabilities of Sidense’s single transistor one-time programmable memory products (1T-OTP). Just to summarize, it is an anti-fuse device that works by permanently rupturing the gate oxide under the bit-cells storage transistor, something that is obviously irreversible. Also, compared to devices that depend on sensing the presence or absence of a charge the read voltages are low and so the memory is naturally low power. The memory does require some non-standard voltages, especially for programming, but these are all internally generated by charge pumps. Another key advantage of the anitfuse approach is that it can be manufactured in a standard digital process with no additional masks or process steps required.
Sidense will be presenting at TSMC’s OIP on October 1st. The technology has been proven in both poly gate and HKMG gate-last. As a result there is broad support for TSMC processes from 40nm down to 20nm (all planar) with FinFET support currently in development. Sidense 1T-OTP has completed IP9000 assessment across many nodes with more coming later this year and next year.
Obviously the picture at the start of this article is a planar process and in FinFET the gate-oxide is around the fin. Nevertheless, the FinFET structures align well with Sidense’s OTP implementation. Compared to 20nm, the 16nm FinFET implementation has the same bit-cell architecture and OTP design, although the bit-cell and macros are smaller, with lower leakage and better performance.
There are also other Sidense products suitable for use in other TSMC processes typically used for analog, mixed-signal, high voltage etc. However, the Sidense memories only depend on the underlying standard digital process.
Betina Hold, director of R&D at Sidense, will be presenting An Antifuse-based Non-Volatile Memory for Advanced Process Nodes and FinFET Technologies at 4.30pm on the IP track (in the unenviable slot between attendees and beer). Register for OIP here. More details on Sidense’s product line here.