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What is inside the iPhone5s? Samsung or TSMC?

What is inside the iPhone5s? Samsung or TSMC?
by Daniel Nenni on 06-26-2013 at 6:00 pm
Categories: GlobalFoundries, TSMC

As a semiconductor professional and an Apple customer I’m very interested to see what is inside the iPhone5s. Rumors are spreading, photos are leaking, creating a nice build up to the next release of the mobile device that changed the world.

Honestly, last year I was a bit disappointed with the iPhone5. Inside is the A6 SoC which uses the Samsung 32nm process technology, even though Samsung announced a fully qualified 28nm process in June of 2011 (Can Samsung Deliver?). As a result, rumors swirled that Apple would switch to TSMC 28nm, rumors which I found to be false (TSMC Apple Rumors Debunked). So no, sad to say the iPhone5s will not have a TSMC 28nm SoC. My guess is that it will be Samsung 28nm which is said to be in production now.

Unless the iPhone5s has some cool new features like finger print scan and NFC for quick coffee house purchases, I will probably wait for the TSMC 20nm powered iPhone6 next year.

The other rumor that came out of Taiwan this week from DigiTimes is that Apple signed an agreement with TSMC for 20nm, 16nm, and 10nm. I’m in Taiwan now and can tell you that NOBODY here takes DigiTimes seriously. Same thing goes for Seeking Alpha, DeepChip, SemiAccurate, and other click hungry rumor websites. TSMC has beefed up security in the recent months so I seriously doubt that type of information leaked out here. Apple is also VERY secretive so I think it is just one of those tabloid journalism attempts to catch your eye.

From my discussions at the 50th Design Automation Conference, the top fabless companies are still looking closely at the different FinFET processes, waiting for the final PDKs (Process Design Kits) to be delivered later this year. Given the capacity issues at 28nm (since only TSMC yielded), I fully expect the fabless industry to keep second and even third source FinFET options open. As for who wins the node with the most first source contracts? It will be a tight race between TSMC, GLOBALFOUNDRIES, and Samsung with wafer price being the critical factor. My bet of course is on TSMC since they have the required capacity for mobile and trust is always part of the wafer purchase equation.

From what I know today, all three foundries will be ready for FinFET tape-outs in Q4 of this year. Here is my personal score card for the top fabless semiconductor companies on where they will manufacture FinFET Devices next year:

[LIST=1]

  • Apple @ TSMC and Samsung
  • Qualcomm @ TSMC, GLOBALFOUNDRIES, Samsung
  • Nvidia @ TSMC and Samsung
  • Xilinx @ TSMC
  • Altera @ Intel
  • Broadcom @ TSMC and GLOBALFOUNDRIES
  • NXP @ TSMC
  • Freescale @ TSMC
  • Mediatek @ TSMC and GLOBALFOUNDRIES
  • Marvell @ Samsung

    This of course is subject to change when the 1.0 production version of the PDKs (Process Design Kits) are released. TSMC could sweep the entire node like they did at 28nm and 20nm. But for someone to say that any of these companies has signed a foundry deal for 10nm is just silly. 10nm negotiations have just started and will absolutely hinge on who delivers 16nm as promised and at what price. All of this is just my opinion of course but let common sense prevail!

    lang: en_US

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    TSMC and Xilinx on the FinFAST Track!

    TSMC and Xilinx on the FinFAST Track!
    by Daniel Nenni on 06-23-2013 at 2:00 am
    Categories: Foundries, FPGA, TSMC

    The power of the fabless semiconductor ecosystem never ceases to amaze me. On one hand you have the Intel backed press crowing about Intel stealing Altera from TSMC. On the other hand you have Xilinx and TSMC crowing about a new ‘one-team’ approach. If you are interested in the real story you’ve come to the right place.

    “Altera’s FPGAs using Intel 14 nm technology will enable customers to design with the most advanced, highest-performing FPGAs in the industry,” said John Daane, president, CEO and chairman of Altera. “In addition, Altera gains a tremendous competitive advantage at the high end in that we are the only major FPGA company with access to this technology.”

    “I am extremely confident that our ‘FinFast’ collaboration with TSMC on 16-nanometer will bring the same leadership results that we enjoyed at previous advanced technologies,” said Moshe Gavrielov, President and CEO of Xilinx. “We are committed to TSMC as the clear foundry leader in every dimension, from process technology to design enablement, service, support, quality, and delivery.”

    The one disadvantage of the fabless semiconductor ecosystem and crowd sourcing in general is that you are working with companies that also work with your competitors. That is certainly the case with TSMC since just about every fabless semiconductor company manufactures at TSMC and TSMC is bound by honor (The Trusted Technology and Capacity Provider) to provide a level playing field for all customers. The only thing worse would be if the company that manufactures your product competes directly with you, just ask Apple!

    “We look forward to collaborating with Altera on manufacturing leading-edge FPGAs, leveraging Intel’s leadership in process technology,” said Brian Krzanich, chief operating officer, Intel. “Next-generation products from Altera require the highest performance and most power-efficient technology available, and Intel is well positioned to provide the most advanced offerings.”

    “We are committed to working with Xilinx to bring the industry’s highest performance and highest integration programmable devices quickly to market,” said Morris Chang, TSMC Chairman and CEO. “Together we will deliver world-class products on TSMC’s 20SoC technology in 2013 and on 16FinFET technology in 2014.”

    This was certainly the case for Altera and Xilinx at TSMC. The flow of information and collaboration was definitely guarded knowing full well that any process improvement would benefit both companies. Altera moving to Intel changed that of course, a change for the better in regards to the greater good of the fabless semiconductor ecosystem. Putting the number one foundry (TSMC) in close collaboration with the number one provider of programmable technologies and devices (Xilinx) could be a serious game changer, absolutely. Look for a Xilinx flavored version of the 16nm process for higher performance applications like FPGAs, CPUs, and GPUs. Just my opinion of course.

    Let’s look at the FUD side of this:

    • Intel as a foundry is an unknown
    • How fast will Altera be able to build a competitive Intel based ecosystem?
    • Intel as an FPGA manufacturer is an unknown
    • Will Intel eat crow and sign an ARM Manufacturing deal? (ARM cores are big in the FPGA world)
    • Or will Intel force Atom on Altera?
    • What happens to the other Intel FPGA partners Tabula and Achronix?

    I’m not questioning Altera’s decision to partner with Intel. It was definitely the right thing to do given Xilinx seriously challenged them at 28nm and will again at 20nm. Competition fuels our industry and Intel/Altera are a competitive threat so it is for the greater good.

    I do however question the Intel biased spin on the situation and the constant bashing of the fabless semiconductor ecosystem. My opinion, Intel will rue the day they openly attacked QCOM, ARM, TSMC, and the rest of the fabless crowd, believe it. Hey Mr. Intel, this is not the microprocessor world you have controlled since the beginning of time. You are not in Kansas anymore Dorothy.

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    Taiwan Semiconductor Tries To Pull A FinFAST One!

    Taiwan Semiconductor Tries To Pull A FinFAST One!
    by Daniel Nenni on 06-16-2013 at 7:00 pm
    Categories: Foundries, TSMC


    This completely misleading title is from a Seeking Alpha (SA) article, a stock investment version of the National Enquirer. As I mentioned inA Call to ARMs, fame and fortune seeking SA Authors make a penny per click so sensationalism sells. The article is not worth your time so I will save you the click and skip to the misguided conclusion:

    TSMC is a great company that is a leader in the foundry space, but they are trying too hard to appease investors/customers with some of these claims regarding FinFETs. On the January call (before Intel took Altera and likely Cisco (CSCO) from TSMC), the claim was “minimal volumes of 16nm in 2015”. Now, TSMC is trying to pull a FinFAST one on investors and customers by claiming that 16nm will be in production during 2014, totally bypassing the yet-to-ramp 20nm node.I’m not buying these claims, and neither should you.

    First, you should know that Cisco is an IBM ASIC customer not a TSMC customer. ASIC customers do the front half of the design while letting the ASIC vendor (IBM) complete the chip. TSMC does not do ASICs, to be a TSMC customer Cisco will have to go through a services provider such as Global Unichip or LSI Logic. IBM is getting out of the ASIC business so Cisco switching to Intel is a smart move. Today Intel does not have the ecosystem required to allow fabless semiconductor companies to use their fabs without training wheels so the ASIC model works for Intel. Seeking Alpha is promoting F.U.D. (fear, uncertainty, and doubt) here.

    Second, here is a FinFET update: As a SemiWiki reader you should know that I have spent a lot of time on FinFETs since hearing about them at ISSCC in 2011:

    “New transistor designs are part of the answer,” said Dr. Jack Sun. “Options include a design called FinFET, which uses multiple gates on each transistor. Researchers have made great progress with FinFET, and TSMC hopes it can be used for the next generation of CMOS — the industry’s standard silicon manufacturing process.”

    Immediately following, I asked friends and co-workers why TSMC did not already have FinFETs on the road map. The answer from the top fabless companies was that changing transistor architecture is a huge risk and the reward of FinFETs was not clear to them at that time. This was back before 28nm when the top mobile designers chose 28nm polyscion over HKMG for the same reason, lower risk. Leading edge semiconductor designers are by nature risk adverse.

    Let us not forget where FinFETs came from: Dr Chenming Hu, the father of FinFETs, and this year’sKaufman Award winner. Chenming’s ground breaking work on FinFETs and the BSIM modeling standard were the highlights of his technical achievements. Chenming is a former TSMC CTO and today is a TSMC Distinguished Professor at UC Berkeley. TSMC knows FinFETs, believe it.

    Disclaimer: The following FinFET information comes from sessions and private discussions at the 50[SUP]th[/SUP] Design Automation Conference this month, not from Googling around and making foolish assumptions to support my stock positions.

    Today the top fabless semiconductor companies have taped-out 20nm designs which will go into production in 2014. 20nm is now ramping, silicon IS correlating (working), I see no barriers to full production in 2014. TSMC estimated that 20nm revenue would start in Q2 2014 but my bet is they are being conservative by one quarter to appease Wall Street. Either way your iPhone6 will have TSMC 20nm Silicon next year, believe it.

    FinFETs are also ahead of schedule. Remember, the first version of FinFETs will use the 20nm process so delivering them in one year versus the standard two year new process technology launch is not unexpected or unrealistic to the experienced semiconductor professional. Consider 16nm to be a half node in regards to development time and delivery.

    Today the 16/14nm version .5 PDKs (process design kits) are in use by the leading fabless semiconductor companies. The 1.0 PDKs will be released in October with tape-outs shortly thereafter. If the PDK change between version .5 and version 1.0 is minimal, tape-outs will happen in Q4 of 2013 with production/revenue STARTING one year later (just in time for the iPhone7). If the 1.0 PDK has significant changes tape-outs may be delayed to Q1 2014. Keep reading SemiWiki and you will be one of the first to know.

    The other interesting FinFET news is that the foundries will most likely offer two versions of the 16/14nm process: a low power version and a version with more performance. From what I understand the transistor thresholds and pitches will be adjusted for performance. Not a big change but hopefully it will get an extra 10% or more speed-up for those who need it.

    So again Seeking Alpha is publishing FinFALSE information to satisfy personal agendas of the Authors. Just my opinion of course.

    lang: en_US

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    Meeting with Sidense at TSMC Technology Symposium

    Meeting with Sidense at TSMC Technology Symposium
    by Eric Esteve on 06-10-2013 at 11:34 am
    Categories: IP, Sidense, TSMC

    If you have attended DAC in Austin (June 2-5), you probably have missed the first TSMC Technology Symposium. It was held on June 6 in Shanghai. Considering my own experience of a 29 hours trip to come back home (in France), I doubt that it was any possible to leave Austin on June 5 to attend TSMC Technology Symposium in Shanghai on June 6, even flying a 2X supersonic airplane (the trap is the 13 hours time difference between both cities – in the wrong direction, leaving only a couple of hours to make it!).
    But, if you want to meet with Sidense at TSMC Technology Symposium, you still can make it if you live close to:

    • Amsterdam, the Symposium will be on June 18
    • Herzliya (Israel), it will be on June 26
    • Yokohama (Tokyo) on June 28

    On a map, Yokohama looks far from Tokyo by car, but if you take the Shinkensen (Japanese High Speed train), you will be surprised how fast you arrive. The point is just to read Japanese characters in Tokyo station to find the right platform, or ask your way, that I did successfully!
    Just remember that Sidense is the OTP NVM IP vendor who has recently won an interesting case as I blogged here: The decision made by United States Court of Appeals for the Federal Circuit, “Affirming” the District Court for the Northern District of California’s summary judgment of non-infringement on Kilopass’ patent claims and its dismissal, with prejudice, of all remaining claims against Sidense, is certainly a good news for IP and EDA vendors playing a fair sales and marketing game in the field. Let’s make the assumption that you have not infringed anybody else rights, but developed innovative product (IP function or EDA tool), be clever enough in marketing the product and generate numerous design win, so your sales revenue start growing fast, leading your direct competitor to prefer using the legal field instead of fair market competition… We have seen many legal cases in the recent years in the EDA and IP ecosystem, and I am almost sure that some of these cases have been initiated to compensate for a marketing weakness.

    To go to TSMC Technology Symposium, just register here, and you could visit Sidense and discuss about OTP NVM IP, much more interesting topic than legal battle.

    Eric Esteve from IPNEST –

    lang: en_US

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    The Morphing of Intel’s Monopoly

    The Morphing of Intel’s Monopoly
    by Ed McKernan on 05-09-2013 at 12:01 am
    Categories: Foundries, Intel Foundry, TSMC

    It was a generation ago when Intel, less than three years old, created the three fundamental building blocks of the compute era: the DRAM, the EPROM and the Microprocessor, an incredible feat of innovation by any measure. Manufacturing yield, not power or performance determined success of failure and in the first two Continue reading “The Morphing of Intel’s Monopoly”

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    IP Quality: Foundation of a Successful Ecosystem

    IP Quality: Foundation of a Successful Ecosystem
    by Eric Esteve on 05-08-2013 at 8:46 am
    Categories: Foundries, IP, TSMC

    Talking about Design IP (I mean successful Design IP) lead you to quickly pronounce the two magic key words: Quality and Ecosystem. Those who remember the IP emergence in the mid 90’s know very well why Quality has to be a prerequisite when dealing with Design IP, as they probably have paid the price of mediocre IP quality at that time. More recently, business analysts have realized that the foundation for a successful IP based business was linked to building a complete Ecosystem, just think about the 1000 ARM partners…

    As a matter of fact, some of these partners are heavyweight, like Taiwan based TSMC, that any IP vendor would like to count within it IP Ecosystem. That’s why TSMC has created, back in 2000, the TSMC9000 program as one of the pillar of Open Integration Platform (OIP) ecosystem. TSMC9000 clearly defined goal is to check for, assess and audit the quality of Design IP part of OIP ecosystem. TSMC9000 is not only based on cleaver communication, but on a very rigorous process! Don’t forget that any of this Design IP function will end up into a very concrete piece of Silicon, an Integrated Circuit, and that both TSMC (who process it into Wafer Fab) and the Fabless customer who plan to sell it, expect this IC to run first time right. As an IP vendor, you submit to TSMC (in fact to “IP Portfolio, Design Infrastructure Division”) the functional IP you have developed, from USB PHY to DDR Memory Controller, LVDS I/O to DSP and many more. TSMC9000 Quality Assurance system consists to run successively:

    • DRC/LVS (if you submit Hard IP)
    • Data Consistency check
    • ESD tolerance verification
    • Design margin verification (Shmoo plot)
    • Then generate Silicon reports (on Test chips) and store production history when it’s relevant.

    Your IP will hopefully be sold to customer, integrated into a design data base by this customer who will finally submit the final DB for Tape Out. At this stage, TSMC will use “IP Master” tool, running “Tape Out consistency checks” versus the previously generated data in IP9000 IP Quality.

    You may wonder that TSMC9000 IP qualification process only applies to very complexes or very specific or “exotic” Design IP… In fact, if you take a look at the above picture, you realize that TSMC9000 apply to ALL the Libraries, Memories or IP, including Hard and Soft IP. How many IP would you guess? Are we talking about 500 Design IP, or 1000, maybe 2000? Just take a look at the statistics listed below…

    There are no less than 8917 active IP coming from the IP Alliance for a total of almost 10, 000 IP in TSMC 9000! Another figure is surprising: almost 200 Design IP are being reviewed every month by TSMC. This means that TSMC has built a specific team 100% dedicated to run IP9000 QA Process, a 30 people team in charge of IP Port-Folio validation (and selection). As an IP vendor, you probably better understand why TSMC has to be highly selective when accepting new IP… Are you still in IP vendor shoes? Just look at the failed TSMC 9000 IP count: 1,452!!

    Even if a dummy density violation or some Silicon corner out of specification can be accounted for a failure, out of these 1,452 IP, as high as 373 can generate potential fatal failure. Fatal simply means that a Tape Out including such IP would have led to a redesign. Thus, if you go now into Fabless shoes, you will just thank your foundry supplier for being so selective!

    If you ever surfed on a foundry web site, you probably remember the “Bronze”, “Silver” and “Gold” denomination for Design IP. If you look at the above picture, these denominations look a little bit obsolete: before a Design Hard IP can be validated for volume production, it has to pass through no less than ten or more verification phases, before the Design IP can reach a high enough confidence level. If we consider advanced nodes, the Hard IP has to pass through 13 various checking phases, from DRC, LVS, ERC and Antenna checks up to Split Lot Silicon Assessment, testing results audits by TSMC test lab to finally go to production. In fact, Quality assessment is a never ending process, when the ASIC or ASSP is in volume production, the IC yield is continuously traced… probably up to the product End Of Life!
    I didn’t know that Quality could be a fascinating topic (to be honest, I thought it was not), but we are working in such demanding industry that even Quality becomes part of the dream: I have today in my pocket a gaming station from the 2000’s, a phone from the 90’s, a color TV from the 80’s and a Supercomputer from the 70’s, all of these almost in a single chip!

    Eric Esteve

    lang: en_US

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    How To Design a TSMC 20nm Chip with Cadence Tools

    How To Design a TSMC 20nm Chip with Cadence Tools
    by Paul McLellan on 05-07-2013 at 8:10 pm
    Categories: Cadence, EDA, Foundries, TSMC

    Every process node these days has a new “gotcha” that designers need to be aware of. In some ways this has always been the case but the changes used to be gradual. But now each process node has something discontinuously different. At 20nm the big change is double patterning. At 14/16nm it is FinFET.

    Rahul Deokar and John Stabenow of Cadence and Jason Chen from TSMC will present, “20nm Design Methodology: A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Encounter, Virtuoso, and Signoff tools.” Well, I think my title gets to the point a bit quicker!


    Double patterning has been forced on us by limitations in lithography. We still use 193nm light even though we are now drawing features that are 20nm (actually there isn’t really anything on a 20nm chip that measures 20nm). If we try and draw all the polygons on the lower layers of the process, the features are too close to print correctly. So instead we have to separate them onto two separate masks, so the polygons in effect alternate. Not all layout can be split in this way, which is usually called coloring since it is basically a graph-coloring algorithm, so routers and designers need to be careful not to create uncolorable layout.

    Sometimes, even (say for analog), the designer wants to color the polygons manually. Why would they do that? At this process node, the two masks are not self-aligning. They are aligned by the vestigials on the wafer that the stepper detects, just like any other mask (actually reticle) but the two polygon layers have some slop in their alignment. This means that there is much tighter control of parasitics between polygons on the same mask (which are automatically self-aligning) and different masks (which are not).

    There are self-aligned double patterning techniques. They use a sacrificial spacer (where both sides of the spacer eventually get whatever is being created on that layer) but they are more expensive. If you want to get a few chapters ahead, we will need to use these approaches to build transistors at the 10nm node (and maybe the lower levels of interconnect) but at 20nm we are not. I’m not sure about 16nm.

    The layout rules for 20nm are very much more restrictive, even without worrying about double patterning. There is a lot less flexibility about what can go where, and weird features like dummy gates that we started to see at 28nm (where an extra poly is required on the end of a gate that is not electrically significant, to ensue that the gate prints and behaves correctly). We also have layout dependent effects (LDE) where the transistor circuit level performance depends on how close the transistor is to other features on the die, especially well boundaries. And even design rules that depend on electrical details. There is also local interconnect that appears between the transistors and the lowest level of true metal, with all its own rules.


    A little more detail on what you will learn:

    • How in-design double patterning technology (DPT) and design rule checking (DRC) can improve your productivity
    • How both colored and colorless methodologies are supported, and data is efficiently managed in front-to-back design flows
    • How local interconnect layers, SAMEMASK rules, and automated odd-cycle loop prevention are supported
    • How mask-shift modeling with multi-value SPEF is supported for extraction, power, and timing signoff.

    The webinar is being given twice on May 23rd at 9am Pacific (early evening in Europe) and at 6.30pm Pacific (morning in Asia). Details here. Registration here.

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    Solido CEO on 20nm/16nm TSMC and GLOBALFOUNDRIES Design Challenges

    Solido CEO on 20nm/16nm TSMC and GLOBALFOUNDRIES Design Challenges
    by Daniel Nenni on 05-04-2013 at 11:00 am
    Categories: EDA, Foundries, GlobalFoundries, Solido, TSMC

    EDA needs more CEOs like Amit Gupta. Solido, which is now profitable, is his second AMS EDA company. The first, Analog Design Automation (ADA), was purchased by Synopsys for a hefty multiplier. Prior to becoming an EDA entrepreneur, Amit was product manager for the wireless group at Nortel and a hardware engineer for the RF communications group at Harris Corporation. I like the Q&A blogs Daniel and Paul do on SemiWiki so here is my first one:

    Q: What are the specific custom IC design challenges your customers are facing?

    We segment the challenges our customers are facing in the following areas:

    [LIST=1]

  • PVT Corner design. PVT variation encompasses process (FF, SS, FS, SF, TT model corners), voltage, temperature, load and parasitic based variation. When taking all the combinations of these parameters, our customers end up having 1000’s or 10,000’s of corner combinations to simulate. The challenge is that to simulate all the corner combinations is accurate, but very slow. Guessing which corners to simulate is faster, but inaccurate.
  • 3-sigma Monte Carlo design. The process model corners that foundries like TSMC or GLOBALFOUNDRIES release in their PDK’s are not well suited to individual designs. They are either overly conservative leading to overdesign, or overly optimistic leading to yield loss. As a result, foundries are now releasing local and global statistical variation models for designers to run Monte Carlo analysis simulation on their designs. However, brute force Monte Carlo SPICE simulation is slow, inefficient, and time consuming to use in the design loop.
  • 6-sigma Monte Carlo design. For designs that are being replicated 1000’s or more times, designing to 6-sigma becomes important. Examples include bit cells for memory design or standard cell library designs. To design to 6-sigma, 5 billion Monte Carlo sample simulations would be needed that would take years and therefore impractical. Alternatively, designers are designing to 3-sigma, and extrapolating to 6-sigma but this methodology is inaccurate. Some companies have developed internal importance sampling techniques, but these don’t scale and suffer from accuracy issues.
  • Variation debug.If the design is failing PVT corner, 3-sigma or 6-sigma Monte Carlo verification steps, designers need to identify the design sensitivities to variation and figure out how to fix the design, making it robust to variation. Manually changing the device sizes and running PVT or Monte Carlo analysis to check whether the changes fix the design is tedious and time consuming.

    As you can see, the common theme is that the number of SPICE simulations required to get complete design coverage is exploding, which is leading designers to compromise accuracy to get their designs out sooner, or compromise design time to get accurate results.

    Our customers are facing these challenges when doing memory, standard cell, lower power and analog/RF design.

    Q: What does Solido Design do?

    Solido provides variation analysis and design software for custom IC’s so that our customers can achieve maximum yield and performance in their designs. Solido’s product, Variation Designer, boosts SPICE simulator efficiency while increasing design coverage. Solido Variation Designer is being used by top semiconductor companies to design memory, standard cell, analog/RF and low power custom IC designs at leading design nodes including TSMC and GLOBALFOUNDRIES 40nm, 28nm, 20nm, 16nm.

    Q: Why did you start Solido?

    This is the second EDA startup I founded – I really enjoy entrepreneurship and the process of starting and building a business to address user challenges. I co-founded Solido in 2005 after my previous company, Analog Design Automation, was acquired by Synopsys. We talked to many companies about upcoming challenges they were facing, and quickly realized that variation in custom IC design was a common theme. We then raised about $10 million in investment capital and worked very closely with lead companies in developing the v1.0 alpha of our product – Solido Variation Designer. Now, we are releasing Solido Variation Designer v3.0 which is in use by top semiconductor companies and qualified by the top foundries.

    Q: How does Solido help with your customers’ custom IC design challenges?

    Our customers use the following capabilities in our Variation Designer product:

    [LIST=1]

  • Fast PVT. Our customers use Fast PVT to automatically figure out which are the worst case corners while simulating only a fraction of the corner combinations. This leads to far fewer simulations than brute force PVT corner analysis without compromising accuracy.
  • Fast Monte Carlo. Our customers use Fast Monte Carlo to cut down the number of simulations to achieve 3-sigma design without compromising accuracy, and extract design specific 3-sigma corners to design to.
  • High-Sigma Monte Carlo (HSMC). Our customers use High-Sigma Monte Carlo to get the 5 billion Monte Carlo accuracy runs in only a few thousand simulations. This is a dramatic reduction in SPICE simulations and improvement in design coverage. Solido High-Sigma Monte Carlo is fast, accurate, scalable and verifiable.
  • DesignSense. Our customers use DesignSense to automatically identify design sensitivities to variation, so that users can quickly make necessary design changes and verify that it’s meeting specifications.

    Overall, while SPICE simulator companies are focused on improving speed, accuracy and capacity of their tools, Solido is complementarily focused on intelligently figuring out what to simulate giving better design coverage in a reduced number of simulations than brute force.

    Q: What are the tool flows your customers are using?

    Our customers use Solido Variation Designer with their SPICE simulator of choice. Variation Designer is integrated with Cadence Spectre/SpectreRF/APS, Synopsys HSPICE/HSIM/FineSim/XA, Mentor Eldo, BDA AFS, Agilent GoldenGate. Through our partnership with Cadence, Solido Variation Designer is integrated with Analog Design Environment (ADE), or alternatively our customers input designs through the command line. Variation Designer is integrated with Platform LSF, Oracle Grid Engine and Runtime Design Automation NetworkComputer to run 10’s or 100’s of simulators in parallel. Finally, Solido is qualified in the TSMC, GLOBALFOUNDRIES and STARC reference flows for variation analysis and design.

    Q: What is the roadmap for Solido?

    We’ve developed a rich custom IC design software platform:

    [LIST=1]

  • Through our vendor partnerships, we have robust integration with design environments, SPICE simulators and cluster distribution tools.
  • Through our foundry partnerships, we have rich PDK integration to read corner, local and global statistical variation and insight into variation effects at advanced nodes.
  • By working closely with our customers, we have developed algorithmic engines in support of user tasks that dramatically reduce the number of simulations without compromising accuracy.

    Going forward we will continue to work with customers and foundries to address advanced node custom IC design challenges. Having a custom IC design software platform allows us to build new capabilities very quickly and efficiently by leveraging our existing software integrations and enhancing, adapting and inventing algorithmic engines.

    Q: Will you be at the Design Automation Conference this year?
    Yes, we will be exhibiting at DAC. Readers can sign up here for a Solido Variation Designer demo: http://www.solidodesign.com/

    Q: Where can readers get more information?
    Some sources of more information:

    [LIST=1]

  • Fast PVT white paper is available for download here: http://www.solidodesign.com/page/fast-pvt/
  • High-Sigma Monte Carlo white paper is available for download here: http://www.solidodesign.com/page/high-sigma-monte-carlo-for-high-yield-and-performance-memory-design/
  • We published a book with Springer called Variation-Aware Custom IC Design: A Hands-on Field Guide. It is available for purchase here: http://www.amazon.com/Variation-Aware-Design-Custom-Integrated-Circuits/dp/146142268X/ref=sr_1_1?s=books&ie=UTF8&qid=1366656282&sr=1-1&keywords=variation-aware+custom+ic+design
  • You can contact Solido directly at info@solidodesign.com.

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    TSMC ♥ Solido

    TSMC ♥ Solido
    by Daniel Nenni on 04-27-2013 at 8:00 am
    Categories: EDA, Foundries, Solido, TSMC

    Process variation has been a top trending term since SemiWiki began as a result of the articles, wikis, and white papers posted on the Solido landing page. Last year Solido and TSMC did a webinar together, an article in EETimes, and Solido released a book on the subject. Process variation is a challenge today at 28nm and it gets worse at 20nm and 16nm so you had better be ready.

    Solido and TSMC recently completed qualification of Solido Variation Designer for 20-nm memory and standard cell designs. Solido’s software provides accurate, scalable and verifiable 6-sigma design coverage on TSMC 20-nm designs in orders-of-magnitude fewer simulations than Monte Carlo analysis.


    Memory bitcells and sense amps are the first design blocks to take advantage of each shrink in process technology. Transistors are now so small that atomic variances directly impact design variation. Monte Carlo, as the standard for statistical analysis, has not been able to scale to the demands of memory design. Alternate solutions are inaccurate, scale poorly and are difficult to verify.

    Consider a 256 Mb SRAM design, which consists of 256M bitcells and 64k sense amps. For the SRAM to yield, the bitcell yield would need to be 6-sigma, and sense amp yield would need to be 4.5-sigma. However, verifying to this sigma would need billions of Monte Carlo samples which is far too slow.

    Solido’s High-Sigma Monte Carlo (HSMC) was shown to overcome the key drawbacks of traditional Monte Carlo analysis, providing:

    • Significantly fewer simulations
    • SPICE and Monte Carlo accurate results in the regions of interest
    • Scalable support on all design blocks used in memory design
    • Verification, for high confidence in results

    Solido’s System Monte Carlo adds yield analysis capability at the array level:

    • Providing fast 3-sigma analysis across the array
    • Leveraging probability density function (PDF) data from cell-level analysis
    • Reporting tradeoffs between performance and yield
    • Fast enough to enable exploration of different array configurations

    Results of running Solido on TSMC 20-nm memory design:

    • Measured bitcell performance to 6.15 sigma

      • Analyzed 12.8 billion Monte Carlo samples in only 5355 simulations
    • Measured sense amp performance to +/- 4.5 sigma

      • Analyzed 3.2 Million MonteCarlo samples in only 2727 simulations
    • Extracted probability density function (PDF) of bitcell and sense amp
    • Measured Monte Carlo based yield on a 64Mb array for 6 different read speeds in 1.5 hours
    • Improved memory specs by 11% to 52%

    Retargeting standard cell libraries to new technologies is expense. It takes lots of simulator licenses and design time, layout has become part of the design loop, and increasing variability makes it difficult to size cells optimally for yield and performance. High-sigma analysis is necessary for the latest process technologies, but needs too many Monte Carlo samples to achieve accuracy and extrapolation with fewer samples is unreliable and inaccurate.

    Cell Optimizer adds automation for sizing standard cells, providing:

    • Full script-based operation
    • Design sizing across multiple corners and testbenches
    • Support for pre- and post-layout netlists
    • Simulator independence

    On the initial TSMC 20-nm standard cell design, 3 out of 4 measurements failed to meet the specification. After sizing, all measures met specification.

    Signup for a DAC demo here:

    http://www.solidodesign.com/

    Solido Design Automation Inc. is a leading provider of variation-aware custom integrated circuit design software. Solido Variation Designer and application packages are used by analog/RF, IO, memory and standard cell digital library designers to improve design performance, parametric yield and designer productivity. Solido has pioneered a proprietary and patent-pending set of algorithms forming the core of its technology.

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