FinFET Design Challenges Exposed!

FinFET Design Challenges Exposed!
by Daniel Nenni on 04-07-2013 at 6:00 pm

The first mention of FinFETs appeared on SemiWiki after the ISSCC conference in 2011. Dr. Jack Sun, TSMC Vice President of R&D and Chief Technology Officer, spoke about the power crisis the semiconductor industry is facing and FinFETs was one of the promising technologies that could help us. Since then, we have posted 100+ related articles with FinFET being the top trending term for search engine traffic coming to SemiWiki in 2012. That is why Dr Chenming Hu, the father of FinFETs, is the covetedKaufman Award winner this year and why I agreed to keynote FinFET day at the EDPS Conference in Monterey this month. They should call them FunFETs because we are certainly having a good time!

Recently I was invited to an informal back yard BBQ with a group of layout people who are working on FinFET test chips. Layout people are a different breed for sure but you will not meet a harder working group in the semiconductor ecosystem, believe it. And FinFETs are not making their life any easier!

My mother was very analytical, a natural born engineer. Unfortunately, in the 1950’s women weren’t encouraged to work outside the home much less become engineers but she did anyway and ended up being a draftsperson working on the Apollo Space program. I remember getting the VIP treatment as a kid at her work place and noticing that the clear majority of her coworkers were women, except management of course.

It was deja vu all over again when I worked with layout groups in Silicon Valley in the early 1980’s. Mostly women, none of which had engineering degrees but, like my dear mother, were engineers at heart and very good at what they did. 30 years later quite a bit has changed with layout groups and tools given that the job is much more difficult with all of the design and manufacturing advances we have seen over the years.

One of the things that has NOT changed however is the Design Rule Manuals (DRMs). They are still the center of the layout universe, they are still in paper or PDF form, and they are a growing problem for layout people. Process technologies are coming at them faster every year. Design rules are much more complicated and change more frequently during the “maturing” period. DRMs are much more cryptic and tape out schedules are staying the same. Clearly DRMs are going to have to change if we are going to continue down this path otherwise schedules will slip, mistakes will be made, layout people will spontaneously combust, not a pretty picture believe me. Adding layout head count will not help either since it takes years to master leading edge layout. In fact that is what has saved us thus far, the depth of experience the average layout person has today.

The change that is coming, the change that has to come, is with the DRMs. As a communication tool between the foundries and the fabless semiconductor companies it is failing. We need to provide the information REQUIRED to efficiently and effectively layout modern semiconductor devices. What we need is an Interactive Design Rule Manual that brings design rules to life! Sound reasonable?


TSMC to Talk About 10nm at Symposium Next Week

TSMC to Talk About 10nm at Symposium Next Week
by Daniel Nenni on 04-02-2013 at 8:05 pm

Given the compressed time between 20nm and 16nm, twelve months versus the industry average twenty four months, it is time to start talking about 10nm, absolutely. Next Tuesday is the 19th annual TSMC Technology Symposium keynoted of course by the Chairman, Dr. Morris Chang.

Join the 2013 TSMC Technology Symposium. Get the latest on:

  • TSMC’s 20nm, 16nm, and below process development status including FinFet and advanced lithography insights
  • TSMC’s new High-Speed Computing, Mobile Communications, and Connectivity & Storage technology development
  • TSMC’s robust Specialty Technology portfolio that includes CMOS Image Sensor (CIS), Embedded Flash, Power IC and MEMS
  • TSMC’s GIGAFAB™ programs and improvements that enhance time-to-volume
  • TSMC’s 18-inch manufacturing technology development
  • TSMC’s Advanced Backend Technology for 3D-IC, CoWoS (Chip-on-Wafer-on-Substrate), and BOT (Bump-on-Trace)
  • New Design Enablement Flows and Design Services on TSMC’s Open Innovation Platform®

REGISTER HERE

TSMC takes this opportunity each year to let customers know what is coming and get feedback on some of the challenges we will face in the coming process technologies. I remember 2 years ago when TSMC asked customers openly if they were ready for FinFETs. The answer was mixed, the mobile folks definitely said yes but the high performance people were not as excited. Here we are, two years later, with FinFET test chips taping out. So yes, these conferences are important. This is the purest form of collaboration and SemiWiki is happy to be part of it.

TSMC will also let us know that 20nm is not just on schedule but EARLY. They have been working around the clock to make sure our iPhone6s arrive on time so don’t expect any 20nm delays. In fact, recent news out of Hsinhcu says TSMC will begin installing 20nm production equipment in Fab 14 two months early of the June 2013 target. 20nm is also the metal fabric for 16nm FinFETs so expect no delays there either.

The COWOS update will be interesting. Liam Madden, Xilinx Vice President of FPGA development, did the keynote at the International Symposium on Physical Systems (ISPD) last month and three-dimensional integration was the focus on the kickoff day. EETimes did a nice write up on it: 3-D Integration Takes Spotlight at ISPD:

“For many years, designers kept digital-logic, -memory and analog functions on separate chips—each taking advantage of different process technologies,” said Madden. “On the other side are system-on-chip [SoC]solutions, which integrate all three functions on the same die. However now there is a third alternative that takes advantage of both worlds—namely 3-D stacking.”


3D transistors plus 3D IC integration will keep the fabless semiconductor moving forward at a rapid pace. If you would like to learn more, Ivo Bolsens, CTO of Xilinx, will be keynoting the Electronic Design Processing Symposium in Monterey, CA this month. The abstract of his keynote is HERE.

There is also a 3D IC panel “Are we there yet?” moderated by Mr 3D IC himself Herb Reiter. Herb will be joined by Dusan Petranovic of Mentor Graphics, Brandon Wang of Cadence, Mike Black of Micron, and Gene Jakubowski of E-System Design. Abstracts are HERE. Register today, room is limited!


TSMC Tapes Out First 64-bit ARM

TSMC Tapes Out First 64-bit ARM
by Paul McLellan on 04-02-2013 at 2:15 am

TSMC announced today that together with ARM they have taped out the first ARM Cortex-A57 64-bit processor on TSMC’s 16nm FinFET technology. The two companies cooperated in the implementation from RTL to tape-out over six months using ARM physical IP, TSMC memory macros, and a commercial 16nm FinFET tool chain enabled by TSMC’s open innovation platform (OIP).

ARM announced the Cortex-A57 along with the new ARMv8 instruction architecture back at the end of October last year, along with the Cortex-A53 which is a low-power implementation. The two cores can be combined in the big.LITTLE configuration to combine high performance with power efficiency.

Since the beginning, ARM processors have been 32 bit, even back when many controllers in markets like mobile were 16 bit or even 8 bit. This is the first of the new era of 64-bit ARM processors. These are targeted at datacenters and cloud computing, and so is a much more head-on move into Intel’s core market. Of course, Intel is also trying, with Atom, to get into mobile where ARM remains the king. I doubt that this processor will be used in mobile for many years. There is a rule of thumb that what is used on the desktop migrates into mobile 5 years later.


TSMC have been working with ARM for several process nodes over many years. At 40nm they had optimized IP. Then at 28nm they taped out a 3GHz ARM Cortex-A9. At 20nm it was a multi-core Cortex-A15. Now, at 16nm, a Cortex-A57.

This semiconductor process is basically one with the power and drive advantages of FinFET transistors, but with the more mature 20nm metal fabric that does not require excessive double patterning and the attendant extra cost. This process is 2X the gate density of 28nm with 30+% speed improvement and power at least 50% less. This 16FF process enters risk-production at the end of this year. Everything needed for doing design from both TSMC and its ecosystem partners is available now for early adopters.

As I talked about last week when Cliff Hou of TSMC presented a keynote at SNUG, modern processes don’t allow all the development to be serialized. The process, the design tools and the IP needs to be developed in parallel. This test chip is a big step, since it is a tapeout of an advanced core very early in the life-cycle of the process. In addition to being a proof of concept it will offer opportunities to learn all the way through the design and manufacturing process.

Last year, TSMC had capacity to produce 15.1 million 8-inch equivalent wafers. If my calculation is correct that is over 1000 acres of silicon. That’s a pretty big farm.


Samsung 28nm Still Does Not Yield?

Samsung 28nm Still Does Not Yield?
by Daniel Nenni on 03-31-2013 at 7:00 pm

As if Samsung didn’t have enough to worry about with their new neighbor to the North (Korea) declaring war, Samsung 28nm is still NOT yielding. In my previous blog “Can Samsung Deliver as Promised?” I wondered what will power the new Galaxy S4 phones that Samsung has been aggressively marketing. You would think it would be a 28nm version of the Exynos 5 Octa SoC that was launched at CES in January with former President Bill Clinton. As it turns out that is not the the case. I like honesty, I like transparency, I don’t like how Samsung is communicating with us on this one.


The first launch of the Galaxy S4 will be powered by 28nm silicon all right, TSMC 28nm silicon in the form of a QCOM Snapdragon 600. That must really hurt the Samsung foundry folks since they are negative selling TSMC and others at the top fabless semiconductor companies in an effort to win 14nm business. At first it was rumored that it was an LTE issue with Exynos but Samsung denied that recently on Twitter of all places. The people I asked here in Silicon Valley, one of which is a Samsung customer, said it was in fact a 28nm manufacturing problem.

Remember, Samsung went Gate-First HKMG instead of Gate-Last like TSMC:

Gate-first HKMG is easier to implement as a transition from a traditional poly/SION structure, she explained. The construction of the gate and transistor remain the same, though the materials are different (i.e., a high-k gate oxide instead of oxynitride); a metal gate is inserted, and then poly on top of that—and the rest of the flow is “basically the same as previous generation structures.” Gate-first also is “much simpler” to implement from a process migration standpoint in terms of IP implementation, and fewer restrictive design rules (gate-last requires CMP around the gate structure). “We can maintain 50% shrink from 45nm to 32nm because there’s not as many restrictive design rules,”Ana Hunter (VP foundry at Samsung Semiconductors)said. This makes the process particularly good for mobile applications, as it’s cost-effective and “very good on gate leakage—a >100× improvement from 45nm to 32nm.”


During one of my Taiwan trips in 2010 I asked Dr. Shang-yi Chiang why TSMC decided on Gate-last versus Gate-first. Shang-yi is TSMC’s Executive Vice President and Co-Chief Operating Officer, he joined TSMC in July 1997 as Vice President of Research and Development (R&D) and has successfully delivered many new process technologies including 28nm. Shang-yi told me quite honestly that TSMC had both Gate-first and Gate-last 28nm HKMG architectures under consideration but concluded that yes Gate-first is simpler (less manufacturing steps) and would be easier to design to (less restrictive) but it was much harder to yield, especially for complex SoCs. The rest is history, TSMC successfully implemented Gate-last 28nm and they have 100% market share as a result.

This all goes to credibility which is the cornerstone of collaboration and the fabless semiconductor ecosystem. Let’s not forget how all this fabless stuff got started. The traditional semiconductor companies (IDMs) were not doing their jobs. They rented out their excess capacity allowing former employees to innovate and bring us companies such as QCOM, BCOM, NVDA, XLNX, and the resulting fabless semiconductor ecosystem.

Now, Intel and Samsung (both IDMs) are trying to get back control of the semiconductor industry and will spend whatever it takes to do so. According to IC Insights, their combined capital expenditures now represent more than 40% of the total semiconductor capital spending. To me this is a great cause for concern for the fabless semiconductor ecosystem. Just my opinion of course.


Mentor at TSMC Technology Symposium

Mentor at TSMC Technology Symposium
by glforte on 03-29-2013 at 11:41 am

TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage, CIS, embedded flash, power ICs, and MEMS.

Mentor Graphics will host a booth at the conference where you can learn more about Mentor’s reference flows, and tools for IC physical design, verification, DFM, silicon testing and yield improvement. Experts will be available to discuss special topics such as advanced fill requirements, double patterning, design for reliability, cell-aware testing and IJTAG.

To learn more and register,click here.


TSMC on Collaboration: JIT Ecosystem Development

TSMC on Collaboration: JIT Ecosystem Development
by Paul McLellan on 03-27-2013 at 2:02 pm

Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry’s Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.

This doesn’t work any more. Since then each process generation has a major discontinuity:

  • 45nm: power must be addressed
  • 28nm: high-K metal gate
  • 20nm: double patterning
  • 16nm: FinFET
  • 10nm: multiple patterning and spacer

These discontinuities mean that foundries such as TSMC have to work closely with EDA suppliers such as Synopsys to ensure that the tools are ready when the process is ready. Otherwise they face the problem of building a $5B fab and not having any designs ready to run in it for a year. For example, without double patterning aware place & route, and layout editors, DRCs etc it is not possible to do a 20nm design.

This is happening in an environment where the number of tapeouts is not increasing, and is probably declining. But the number of wafers needed in production is increasing exponentially. This makes it critically important to hit the volume and yield-learning ramps for a new process. Wafers that are not manufactured don’t really come back, the end-user will have purchased another product. TSMC is increasing its capacity at a 31% CAGR. That’s a lot of wafer starts. Better make sure there are really wafers to start.

Another factor that has been growing in importance is the increasing use of IP in SoC designs. This means that not only do EDA tools need to be ready to go when the process is ready, but IP needs to be ready too. It is hard to do an SoC design without DDRx, PCIe, USB and so on.


So TSMC needs to have 3 parallel collaboration tracks:

  • working with EDA suppliers to ensure that the gotcha new features such as double patterning or FinFETs in the new process have full support in the tools
  • working with IP suppliers to ensure that IP is ready in a timely manner. It may not be possible to have all IP available when the process is ready, for both technical (IP suppliers need the tools and the process to be reasonably stable to get work done) and economic (there is a lot of IP and it can’t all be created in parallel
  • working with lead design groups to ensure that the process matches their needs, that they have the PDKs and design kits they require and so on

The goal is to have everything come together so that when the process is ready and the fab is ready to ramp to volume, that the designs are there. In turn that requires IP and tools to be there to get the designs done.


The next process, 16nm, is a FinFET process so the new challenges largely are around the transistors (the metal fabric is basically unchanged from 20nm). Although FinFETs are wonderful from some points of view (low leakage, high current, lower voltage) they have some disadvantages too (higher parasitic capacitance, higher parasitic resistance due to the MEOL local interconnect, quantized device widths). The biggest challenge has probably been RC extraction accuracy, although that seems to be as good with FinFET as at 28nm now.

The goal for future processes is:

  • around 2X increase in gate-density per node. With no EUV at 10nm this will get challenging
  • 15% speedup with 25% power reduction per node. This should be easier than the area reduction
  • And although Cliff didn’t mention it, another major challenge is to keep the cost per wafer in line so that the 2X increase in gate-density also shows up as a cost reduction

So collaboration within the TSMC Open Innovation Platform (OIP) is the only way to address these types of challenge and get everyone to the finish line at the same time.

And with that, Cliff Hou went to get on a plane back to Taiwan having only flown in yesterday!


Unlocking the Full Potential of Soft IP

Unlocking the Full Potential of Soft IP
by Daniel Payne on 03-22-2013 at 11:32 am

EDA vendors, IP suppliers and Foundries provide an eco-system for SoC designers to use in getting their new electronic products to market quicker and at a lower cost. An example of this eco-system are three companies (TSMC, Atrenta, Sonics) that teamed up to produce a webinar earlier in March called: Unlocking the Full Potential of Soft IP.


Continue reading “Unlocking the Full Potential of Soft IP”


Synopsys ♥ TSMC!

Synopsys ♥ TSMC!
by Daniel Nenni on 03-14-2013 at 8:00 am

Dr. Paul McLellan and I will be covering the Silicon Valley SNUG live again this year. Unfortunately we are only allowed to see the keynotes (same thing with CDNLive) but they look very good:

Keynote Address: Massive Innovation and Collaboration into the “GigaScale” Age!
Aart de Geus, Chairman and co-CEO, Synopsys, Inc.

The semiconductor industry is on the bridge to a new world of complexity empowered by smaller dimensions, new transistor types, enormous IP reuse, and a focus on the great potential of electronic systems. In other words, the GigaScale Age is upon us! In addition, our customers are facing uncertain markets where merely making a better version of their last product is not sufficient. To survive and thrive in new and unknown markets, designers and their ecosystem partners are accelerating both their innovation and their collaboration with key partners. They expect the same from their EDA, IP and services partners. In his presentation, Aart will give an overview of the enormous amount of recent innovation and collaboration happening at Synopsys as we enable “Moore’s Law plus, plus” for yet another decade!

Technology Keynote – “From Crystal Ball to Reality — The impact of Silicon IP on SoC Design”
Sir Hossein Yassaie, PhD, Chief Executive Officer, Imagination Technologies Group

SoCs have transformed the semiconductor and electronics industries, integrating staggering breadth of functionality and performance into highly cost-effective, low power but complex single-chip solution platforms. However, there has been another transformation: many of the major functional blocks on today’s SoCs are provided by Silicon IP providers rather than designed in-house. Hossein will review some of the important technological and market trends in key segments and discuss how the IP industry is helping to create the ability to translate vision into reality , and to constantly enhance it. He will touch on key functional blocks in modern SoCs explaining how the GPU is becoming the new driving force not only for modern applications but also for design methodologies and process technologies, and how heterogeneous processing is transforming the way SoCs handle key user applications such as UI’s, gaming, multimedia and more.

Technology Keynote – “Collaborate to Innovate – A Foundry’s Perspective on Ecosystem
Dr. Cliff Hou, Vice President, Research & Development, TSMC

Ecosystem refers to a symbiotic, co-dependent, co-evolutionary and multiplicative relationship among its constituents. The semiconductor industry represents one of the largest business ecosystems in the world where the collective diversity and creativity has fundamentally reshaped the human society. As process scaling continues toward the atomic level, challenges abound and stakes are never higher. In this talk, we will offer a foundry perspective of the semiconductor ecosystem and how, through close collaboration, we combine individual specialties and resources to innovate and move the industry forward. Specifically, we will discuss how the collaboration with EDA is becoming ever closer, earlier and wider to enable designs concurrently with process development, even especially at the advanced nodes.

SNUG Around the world:
[TABLE]
|-
| Silicon Valley
| March 25-27, 2013
|-
| Boston
| September 12, 2013
|-
| Austin
| September 18, 2013
|-
| Canada
| October 1, 2013
|-
| Germany
| May 14, 2013
|-
| United Kingdom
| May 16, 2013
|-
| France
| June 11, 2013
|-
| Israel
| June 18, 2013
|-
| India
| June 12-13, 2013
|-
| Japan
| July 12, 2013
|-
| China
| August 22, 2013
|-
| Taiwan
| August 20-21, 2013
|-
| Singapore
| August 16, 2013
|-

As I mentioned in my blog Synopsys ♥ FinFETs, Synopsys knows FinFETs so be sure to see the FinFET tracks. Paul and I also get to attend the press lunch and hopefully, like last year, an hour roundtable with Aart. It is a great experience to hang with semiconductor people wearing SemiWiki shirts and to get recognized and even photographed. My wife rolls her eyes when it happens and makes me take out the trash when I get home to keep me grounded. But seriously, we all appreciate your support and encouragement and it is a pleasure to collaborate with you.

Note: TSMC’s Dr. Cliff Hou gets a coveted keynote so clearly Synopsys loves TSMC! Cliff would be a great addition to the Synopsys board dontcha think? I will see what I can do…..

Since 1991, SNUG (the Synopsys Users Group) has represented a global design community focused on accelerating innovation. Today, as the electronics industry’s largest user conference, SNUG brings together nearly 9,000 Synopsys tool and technology users across North America, Europe, Asia and Japan. In addition to peer-reviewed technical papers and insightful keynotes from industry leaders, SNUG provides a unique opportunity to connect with Synopsys executives, Synopsys design ecosystem partners and members of your local design community. Join your fellow engineers at the SNUG in your region — you’ll leave with practical information you can use on your current projects and the inspiration to accelerate innovation.


Qualcomm and Intel Dynasty Scenario at 14nm

Qualcomm and Intel Dynasty Scenario at 14nm
by Ed McKernan on 03-08-2013 at 1:00 pm

At a different time, but certainly within the past 12 months, Paul Otellini was asked if Intel would be a Foundry for Qualcomm. His reply was that it did not leave a good taste in his mouth. Nevertheless it was not rejected and the door that remained open just a crack is likely to swing open for Qualcomm, the premier mobile silicon supplier in whom both Apple and Samsung are dependent, to win the Mobile Market. The hinge of fate rests in the hands of Andy Bryant, Chairman of Intel, who would need to EOL the Atom and the acquired Infineon baseband group to eliminate the competitive wall that would lead to not just a true Fab filling but would redraw the geopolitical map of the semiconductor industry. With Intel pouring another $13B of CapEx into its expanded 14nm footprint, there are only two possibilities that make sense: Qualcomm and Apple (the latter is now focused on TSMC). A marriage of Qualcomm baseband with Intel 14nm process technology could result in a scenario that would be a remake of Intel’s 1990s Pentium Dynasty.

The trend in the mobile industry for Samsung and Apple is to continue down the path of increased verticality. The Baseband Ecosystem maintains the high ground in tablets and smartphones and soon it will be a standard feature in x86 ultrabooks. Intel bought Infineon’s baseband group to complete the platform needed to compete in the broader mobile market. However, their efforts are still markedly behind that of Qualcomm and others. Bryant can continue the forced march with little to show or abandon the effort that blocks Qualcomm’s entry into the Fabs.

An article recently mentioned that Apple has hired a team of over 100 ex TI Engineers in Israel to create WiFi and Bluetooth solutions. The timeframe for these solutions is unknown but with $137B in the bank it is easy for Apple to acquire the talent that can create silicon solutions that end up replacing their current suppliers (i.e. Broadcom and Qualcomm). A net reduction of $20 of silicon in every iPhone, iPAD and perhaps Mac Airs could lead to saving the company up to $10B in the era of the Billion Unit+ mobile market that is arriving in the next couple of years. As they say a Billion here, a Billion there and pretty soon your talking real money.

The aggressiveness of Apple and Samsung in designing the key platform components while elbowing out other Fabless vendors at the Foundry has to be making Qualcomm nervous. The $25B+ in Qualcomm’s bank account leads all mobile players, except Apple. What if the cash is not enough of a cushion to prevent Apple or Samsung from hiring or buying the assets of Qualcomm’s competitors? If you think it unlikely, then one just has to review the staggering opportunity outlined above.

Under the Andy Bryant Regime, All product groups must now come clean on their true ROI of existing and new products. Atom processors fall way below the line of pulling their weight for a company that by next January will have spent $36B on Capex in the past three years. All of this to drive towards 22nm and 14nm dominance. In contrast to Atom, the Xeon and Ivy Bridge more than any other digital IC, except FPGAs, are delivering on a heavy positive cash flow. However, the dilemma in play is that mobile will be at least an order of magnitude larger than x86 powered PCs and the number of Fabs will matter in the end game.

The idea that a fast growing market could be on an accelerating path towards consolidation seems at odds with the concept that a rising tide lifts all boats. It took more than 50 years for the American auto industry to consolidate and yet the new mobile industry and the entire supply base may do so in less than 8 years from the time of the first iPhone introduction. It is in Apple and Samsung’s interest to accelerate the trend.

Juxtaposed to the Samsung and Apple vertical supply chain is the also heavily capitalized Fabs of Samsung, TSMC and Intel who race to be the ultimate winner at the leading edge, where all mobile silicon goes to maximize performance/watt while minimizing quiescent current. Intel’s leadership in the pre-mobile days was based on the x86 processor lock required for Windows and its process lead. The silicon supremacy shift away from processors and to the baseband and wireless infrastructure occurred faster than most imagined and the Intel acquisition of Infineon has proved to be too late in the game to help x86 Atoms make a dent in the market.

Now that the multi-billion unit, 4G enabled train has left the station, Intel has to catch up with its only true weapon and that is 14nm. Should Andy Bryant be able to sign a Foundry agreement with Qualcomm and redirect Intel’s massive design resources, there would be benefits in a number of areas for both companies. For Qualcomm, the ability to leverage Intel’s lower cost and much lower power 14nm would remove the competitive threats of Broadcom, nVidia, Mediatek and others. Samsung and Apple would have to think twice of continuing with their own internal wireless and baseband developments as Qualcomm moves into the mid range and low end markets at generous margins. The profit pool that would arise for Intel and Qualcomm would be staggering but it requires Intel give up its desire to own the chip inside the smartphone.

In return for enabling Qualcomm to clear the field, Intel would take a giant step towards rebalancing its Fabs relative to Samsung and TSMC in the mobile market. This move, with Qualcomm’s increased TAM exposure at the expense of its rivals, would be the equivalent of moving more than one Fab loading from TSMC over to Intel’s side of the ledger. For Intel the legacy x86 and Data Center business will still require some leading edge capacity, however a larger and larger percentage of processors will shift to a longer tail business model now that AMD competition has melted away. Intel will initiate other long tail fab deals, of which the 14nm Altera one is a perfect example.

The outcries from the former Otellini regime will be huge as the Atom and Infineon groups fight to remain relevant. The math is simple for Bryant. A $15 Atom processor at 5-10% or even 20% share in the smartphone market doesn’t come close to the revenue and margins that are available by opening up the Foundry to Qualcomm. Legacy Intel and Windows will remain together from tablets to PCs and servers as Win RT on ARM fades quickly into the sunset. By the end of 2013, I can envision a scenario where the partnership of Intel and Qualcomm is announced and the surprise to most is that they are no longer competitors at the platform level.

The tremors that will ripple through the semiconductor industry on an Intel – Qualcomm partnership will destabilize much of the mobile market and over time be seen as greater in magnitude than any other single event, including IBM’s selection of Intel’s 8088 for the original PC that sent Motorola packing. Qualcomm building products at Intel will lay low their wireless peers while Samsung and Apple take time to reconsider if their internal efforts are effectively moot. Intel’s ability to finally monetize its leading edge process will force Wall St. analysts to reconsider their valuation metrics. Beyond this though are additional second order derivatives acting as forcing functions. Will Apple consider a partnership at Intel so that they can develop the equivalent of a Snapdragon with their own ARM processor integrated with Qualcomm’s baseband?

For those of us who have watched the Semiconductor paint dry during the post Y2K decade, it is very interesting to consider what changes may occur as 14nm rolls out.

Full Disclosure: I am Long AAPL, QCOM, ALTR, INTC


TSMC ♥ Atrenta (Soft IP Webinar)

TSMC ♥ Atrenta (Soft IP Webinar)
by Daniel Nenni on 03-02-2013 at 4:00 pm

Back in 2011, TSMC announced it was extending its IP Alliance Program to include soft, or synthesizable IP. Around that time it was also announced that Atrenta’s SpyGlass platform would be used as the sole analysis tool to verify the completeness and quality of soft IP before being admitted to the program. Since then, the program has grown quite a bit. At present, I believe TSMC is closing in on 20 IP Partners that have qualified for inclusion in the program.

Why would TSMC want to focus on soft IP, and why the love affair with Atrenta? If you dig a little, it all makes sense. The third-party IP content in most chips today is 80 percent or more. The winner is no longer the company with the most novel circuit design, it’s the company who picks the best IP and successfully integrates it first. Because of the need for competitive differentiation, soft IP is becoming the preferred technology. You can tweak the content or function of soft IP; it’s a lot harder to do that with hard IP.

“Atrenta will be known for its relentless focus to deliver high quality, innovative products that help to enable design of the most advanced electronic products in the world. Our customers routinely benefit from improved quality, predictability and reduced cost. We maximize value for every customer, employee and shareholder.

So TSMC is on to something. Why not close the customer earlier in the design flow? If I have a choice of two foundry vendors, and one tells me about soft IP quality and one doesn’t, I know who I’m calling back. In sales terms, TSMC is expanding the reach of their “funnel”. So why is SpyGlass the only tool used at the top of that funnel? The aforementioned love affair between TSMC and Atrenta seems to be based on a one-stop shopping approach. TSMC’s quality check for its Soft IP Alliance looks at a lot – power, test, routing congestion, timing, potential synthesis issues and more. SpyGlass has been around a long time and covers all of those requirements. The other option is to work with multiple vendors to get the same coverage. It seems to me as long as SpyGlass is giving reliable answers, it will continue to be the sole tool at the gate to the Soft IP Alliance.

This doesn’t necessarily say Atrenta has a monopoly on the program. TSMC recently announced an endorsement of OaSys as another tool in the Soft IP program, see TSMC ♥ Oasys. I expect more such announcements. It’s a good idea for Soft IP suppliers to have multiple options to help achieve the quality and completeness TSMC is requiring.

If you want to learn more about what TSMC is up to with this program, I’m moderating a Webinar on March 5th that will cover all the details. See Unlocking the Full Potential of Soft IP (Webinar)for more information.

Agenda:

  • Moderator opening remarks – Daniel Nenni (SemiWiki)
  • The TSMC Soft IP Alliance Program – structure, goals and results – (Dan Kochpatcharin, TSMC)
  • Implementing the program with the Atrenta IP Kit – (Mike Gianfagna, Atrenta)
  • Practical results of program participation – (John Bainbridge, Sonics)
  • Questions from the audience (10 min)

Anyone who is contemplating the use of soft IP for their next SoC project should attend this webinar, absolutely!