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December 18, 2013June 14, 2019

TSMC: 3D, 450mm, CoWoS and More

TSMC: 3D, 450mm, CoWoS and More
by Paul McLellan on 12-18-2013 at 4:29 pm
Categories: Foundries, TSMC

The first keynote at the Burlingame 3D conference was by Doug Yu of TSMC. Not surprisingly he was talking about 3D. In particular, TSMC has WLSI technology that they call CoWoS, which stands for chip-on-wafer-on-substrate which pretty much describes how it is built. This is the technology that Xilinx uses for its recently announced high end arrays which I already wrote about here.

The basic driver, in Doug’s view, is that on-chip interconnect is not scaling with Moore’s Law and so alternative approaches are required. He didn’t talk about cost (the manufacturers rarely do but when they talk about higher performance and lower power and don’t mention cost then you have to know the news is not wonderful. At best 20nm is flat to 28nm cost wise).

Another issue is that at 16nm FinFET it is not clear that everything we used to be able to integrate onto a chip, such as RF and analog, will still work. At least at acceptable cost. One obvious advantage of any sort of 3D chip is the ability to mix die from different processes, such as having a 28nm didital chip with 90nm RF/analog (what Doug calls “a ranch in the middle of Manhattan”) and move the 10um inductor off-chip. This saves chip area, cost and power.

TSMC is looking at how to ramp this 3D technology fast to volume. The costs of CoWoS are still too high but there is not really any substitute for the type of yield learning that comes from building products at volume. TSMC sees their goal to grow from a chip foundry to a subsystem foundry, delivering integrated subsystems consisting of die from multiple processes integrated together using CoWoS. He thinks that there are at most 5 companies that could potentially be suppliers into this market.

During questions he was asked about TSMC’s views on TSV holes. There are a number of ways of building TSVs. Via first means that the TSVs are created before the first layer of metal (I don’t think it is possible to do them before the transistors due to the high temperatures used in the FEOL, but I am certainly not a process expert). Via middle means that some metal is created and then the TSV is added and additional metal layers later to hook everything up. It is also possible to create the via from the backside of the wafer. The TSMC view is to do the TSVs as early as possible. Someone pointed out that you cannot use copper for the TSV if you do via first but Doug said that was not true and TSMC uses it today.

Eventually TSMC will scale all this to 450mm but it is too hard to move to 450mm at the same time as a node-change, so that 450mm will first be introduced on a node that is already running at volume. 28nm is my guess. But for wafer scale integration like CoWoS then 450mm is ideal since the costs are lower and they are not trying to get critical features to yield right out at the edge of the wafer where everything is more difficult.

The general impression from the keynotes at 3D ASIP was that:

3D (which really means 2.5D and memory stacks for now) is real and 2014 will start to ramp
costs will come down with yield learning once a few million units have been built and shipped
driver will be high end initially (HPC, networking) not mobile, but mobile is the dream to really drive volume
the biggest problem is, surprisingly, not the TSVs but bond of the wafer onto a substrate for thinning, and then debonding the thin wafer afterwards and all the handling
interposers will have more than wires on. Once costs come down it makes no sense to leave the I/Os on a 20nm die instead of putting them on the interposers (they don’t really shrink anyway). Also power transistors, capacitors etc. If only wires, organic substrates will probably win.
component cost of a 3D chip will not be less than multiple components but the saving at the system level might be very large

QCOM delivers first TSMC 20nm mobile chips!

QCOM delivers first TSMC 20nm mobile chips!
by Daniel Nenni on 11-21-2013 at 3:00 pm
Categories: Foundries, Intel Foundry, TSMC

QCOM is now sampling the TSMC 20nm version of its market dominating Gobi LTE modem. The announcement also included a new turbo charged version of their 28nm Snapdragon 800 SoC with a Krait 450 quad core CPU and Adrino 420 GPU. Given the comparable benchmarks between the Intel 22nm SoC and the 28nm SoCs from Apple and QCOM, the new 20nm mobile products from the top fabless semiconductor companies will be well beyond Intel’s 22nm reach, absolutely.

The question is: When will Intel have a competitive 14nm SoC? The answer will hopefully come today at the Intel Analyst conference so stay tuned to SemiWiki. I will compare the conference info with what I have heard and see how they match up. Spoiler alert: Production Intel 14nm SoCs will not arrive until 2015, believe it.

TSMC’s 20nm process technology can provide 30 percent higher speed, 1.9 times the density, or 25 percent less power than its 28nm technology. The advanced 20nm technology demonstrates double digit 112Mb SRAM yield. The high performance device equipped with second generation gate-last HKMG and third generation Silicon Germanium (SiGe) strain technology. By leveraging the experience of 28nm technology, TSMC’s 20nm process can further optimize Backend-of Line (BEOL) technology options and deep collaboration with customers to continue the Moores’ Law shrinking path. Technology and design innovation keep production costs in check.

The new QCOM Krait 450 quad-core SoC is the first mobile CPU capable of running at speeds of up to 2.5GHz per core with a memory bandwidth of 25.6GB/s which will significantly increase the speed of running apps and browsing the internet. According to QCOM it is also capable of delivering Ultra HD (4K) resolution video, images, and graphics to mobile devices and HDTVs via their new Adreno graphics engine (the Adreno 420 GPU claims a 40% graphics boost over the Snapdragon 800). QCOM also claims to have integrated hardware accelerated image stabilization, which would be an industry first. The quad core processors are still 32-bit which was a bit of a disappointment for me. If anyone can push Android to 64-bit it is QCOM. As it turns out, Apple really did pull a rabbit out of the hat with their 64-bit ARM based A7 SoC for the iPhone5s which I have and am thoroughly enjoying!

“Using a smartphone or tablet powered by Snapdragon 805 processor is like having an UltraHD home theater in your pocket, with 4K video, imaging and graphics, all built for mobile,” said Murthy Renduchintala, executive vice president, Qualcomm Technologies, Inc., and co-president, QCT. “We’re delivering the mobile industry’s first truly end-to-end Ultra HD solution, and coupled with our industry leading Gobi LTE modems and RF transceivers, streaming and watching content at 4K resolution will finally be possible.”

The FinFET version of Snapdragon and Gobi LTE modems are expected to sample one year from now with a 20% performance boost or a 35% power savings from the silicon alone. I also expect it will have a 64-bit ARM based architecture for greater throughput. Apple’s next A8 SoC (iPhone6) is also TSMC 20nm which will mark the first time Apple has competitive silicon with competing tablets and smartphones. Apple’s A7, which just came out, is old school 28nm and last year’s A6 was 32nm. Exciting times in the fabless semiconductor ecosystem, absolutely!

See the Qualcomm presentation HERE.

Xilinx Begins Shipping TSMC 20nm FPGAs!

Xilinx Begins Shipping TSMC 20nm FPGAs!
by Daniel Nenni on 11-11-2013 at 10:00 am
Categories: FPGA, TSMC, Xilinx

Xilinx just announced the shipment of the first TSMC based 20 nm FPGAs, beating Altera to the punch yet again. Xilinx was also the first to ship TSMC 28nm FPGAs and will undoubtedly beat Altera to 14nm which could be the knockout punch we have all been waiting for. The Xilinx UltraScale is a new family of FPGAs that will use 20nm and 16nm processes with 20nm samples available just in time for Christmas! Ho ho ho…

“This announcement underscores our first-to-market leadership commitment of delivering high-performance FPGAs,” said Victor Peng, senior vice president and general manager of products at Xilinx. “The next generation starts now with the shipment of our new UltraScale devices, building upon the tremendous momentum we have established with our 7 series.”

“The delivery of UltraScale devices on TSMC’s 20nm process technology marks a new juncture for the semiconductor industry,” said TSMC vice president of R&D, Dr. Y.J. Mii. “We are happy to see Xilinx continue to break new ground and deliver 20nm silicon to its customers.”

In 2012 the FPGA market was about a $4.5 billion business. Xilinx has about 50% market share at $2.2 billion. Altera is not far behind at $1.8 billion. Being the first to silicon is key in the FPGA world as it not only builds market share, it also builds trust that Xilinx can continue to deliver leading edge products.

Xilinx and longtime manufacturing partner UMC were about one year late at 40nm which allowed Altera and manufacturing partner TSMC to gain significant FPGA market share. Xilinx then switched to TSMC at 28nm and the race with Altera on a level manufacturing playing field began. Clearly Xilinx won 28nm with not only first silicon shipped but also first to 3D IC technology.

One of the big questions I see around the internet is: “Why did Altera really switch to Intel for 14nm?” Simple: Because Altera cannot beat Xilinx to market on a level manufacturing playing field. Even though Altera is a long time TSMC partner, TSMC does not play favorites and delivered technology to both Altera and Xilinx in a uniform manner.

As previously reported, Intel 14nm is late. Word from Altera is that they won’t start taping out 14nm designs until Q4 2014. Xilinx, on the other hand, is taping out 16nm designs early in Q1 2014. Intel is not talking in detail about the speed and density of 14nm in regards to their foundry business so I have no idea how competitive Altera will be against Xilinx at 14nm. But Altera being a year or more late to market is 40nm all over again.

Xilinx and TSMC: Volume Production of 3D Parts

Xilinx and TSMC: Volume Production of 3D Parts
by Paul McLellan on 11-07-2013 at 1:23 pm
Categories: FPGA, TSMC, Xilinx

A couple of weeks ago, Xilinx and TSMC announced the production release of the Virtex-7 HT family, the industry’s first heterogeneous 3D ICs in production. With this milestone, all Xilinx 28nm 3D IC families are now in volume production. These 28nm devices were developed on TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) 3D IC process.

A couple of years ago Xilinx announced what was then the first production part using a 2.5D silicon interposer. The part consisted of four rectangular die on a square silicon interposer. The die were regular FPGA die, flipped onto the interposer. The interposer had routing and through-silicon-vias (TSVs) to power up and connected the four die. It was a huge part. At a 3D symposium in 2011 eSilicon ran the publicly available information about this part through their cost model and reckoned yield would go from 25% for a huge square die to 75% with the smaller rectangular die. Even with the cost of the interposer eSilicon reckoned the cost saving to be around 50%. This was a very high end Xilinx part that apparently has a list price of tens of thousands of dollars, so even though it was in production, the volumes would have been very limited. Plus it was not a heterogeneous 3D design, all four slices were identical. I am sure Xilinx made this part not just because it was cost-effective but as a pipe-cleaner for interposer-based FPGAs and I’m sure they learned a lot.

The significance of 3D is two fold. Firstly, it allows Xilinx to manufacture FPGAs that are too big to do monolithically. Remember that as die size increases, you get fewer die per wafer but also the chance of an entire FPGA avoiding a critical defect decreases exponentially. You don’t avoid the first cost kicker by doing 3D, the die per wafer decreases whether you do multiple small die or one big one. Actually that is not quite true, there are probably some improvements around the edge of the wafer where a little less of the silicon out there is wasted. However, the second cost can be a big difference, with the smaller die yielding very much higher than the large one that might barely yield at all. For some applications, such as SoC prototyping, having a very big array is a big advantage over multiple smaller arrays since it avoids having to partition the SoC design and worry about the very different timing paths between arrays compared to on-array.

However the other significance is that by mixing die (and probably process) Xilinx can make parts like the Virtex-7 H580T which in addition to the array contains sixteen 28Gbps transceivers meaning that you can drive a 100Gbps optical module using only four transceivers compared to ten 10Gbps that you would need on a normal (not heterogeneous 3D) FPGA. That is what makes these parts the first heterogeneous 3D designs in volume production.

The Xilinx press release with more details is here.

TSMC on Semiconductor IP Quality

TSMC on Semiconductor IP Quality
by Daniel Nenni on 11-07-2013 at 9:00 am
Categories: Foundries, TSMC

It is important to note that the System On Chip (SoC) revolution that is currently driving mobile electronics has one very important enabling technology and that is Semiconductor Intellectual Property. Where would we be without the commercial IP market segment? Computers and phones would still be on our desks for one thing, and our appliances certainly would not be talking to us. Semiconductor IP; soft cores, hard cores, foundation IP, interface IP, etc… not only reduce the cost and time to market of SoCs, it also dramatically raises the innovation bar via competition.

Don’t ever forget that TSMC is in the business of selling wafers and IP is a key enabler which is why TSMC spends an incredible amount of time and money on IP quality. A bad IP block can delay or even kill a wafer sale, right? Dan Kochpatcharin, Deputy Director, IP Portfolio Management at TSMC, presented some interesting IP Quality data at the Semico Impact Conference this week. You can find the slides HERE.

“Nobody in this room makes money until the IP comes together on a piece of silicon in production. TSMC’s role is to help host the ecosystem for interoperability, quality, and availability, so that our customers can deliver products. That is what OIP and the TSMC9000 IP quality program is all about.”

The TSMC9000 program consists of a set of rigorous quality requirements for IP designed for TSMC process technologies. Members of the TSMC “Grand Alliance” submit reports and test chip results. This data is available on-line enabling customers to better judge the quality and risk level of the IP before integrating it into their design. Taking IP quality a step further, TSMC has an IP Validation Center (staffed by 30+ TSMC employees) which audits silicon testchip results. This effort is all about trust and clearly in support of the TSMC credo:

Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come.

If you look at the IP usage trends over the last five process nodes (65nm, 40nm, 28nm, 20nm, 16nm) the number of unique IP per tape-out is increasing while the ability to re-use IP across nodes is dropping. And thanks to the ultracompetitive mobile market with new products coming at us everyday, design cycles are incredibly short and complex. Do you really want to spend your precious time and resources qualifying IP? Even worse, do you want to risk integrating one of the many pieces of IP into your SoC that does NOT pass TSMC9000 scrutiny?

The fabless semiconductor ecosystem started with TSMC more than 25 years ago and today it is a force of nature that no one company can control. Hundreds of companies, thousands of products, hundreds of thousands of people, and more than a trillion dollars in yearly investment drive this ecosystem and there is no stopping it, absolutely. You will be able to read more about IP and the fabless ecosystem in the soon to be bestselling book “Fabless: The Transition of the Semiconductor Industry” which can be previewed HERE.

TSMC Continues To Fire On All Cylinders

TSMC Continues To Fire On All Cylinders
by Ashraf Eassa on 10-17-2013 at 5:03 pm
Categories: Foundries, TSMC

Taiwan Semiconductor Manufacturing Corporation is the world’s leading semiconductor foundry by revenue and, by extension, profitability. While I am deeply saddened that current CEO Morris Chang will be retiring (again) shortly, I am hopeful that his successor will be able to continue the legacy of foundry industry leadership that the company has shown over the last few years. With that in mind, I’d like dig into the most recent quarterly report and the accompanying earnings call to try to construct a better picture of what TSMC’s near and long-term future looks like.

There’s No Stopping This Freight Train

TSMC reported a great quarter. Sales were up 14.9% on a year-over-year comparison (remember, year-over-year comparisons are the important ones to make in order to strip away the effects of seasonality), gross margins were 48.5% (just about what one would expect) and operating margin was 36.7% with net profit margin at 32%. Even with dramatically increased R&D and capital expenditures, TSMC continues to manage its expenses commensurate with its revenue growth.

Now, while TSMC’s management has been excellent in doing what it needs to in order to win in this space (outperforming the broader semiconductor industry), it’s also important to note that the company is very levered to the high growth, high-stakes areas of the semiconductor industry. In particular, TSMC has been a prime beneficiary of the mobile computing industry as a good chunk of the chips that go into phones get built at TSMC. Like ARM, TSMC is protected from the booms and busts of particular end customers and is instead levered to the industry as a whole.

The one and only sore-spot of this call was guidance for a sequential decline in Q4 and comments that the high end smartphone and tablet businesses are seeing slowing growth. This was inevitable (nothing grows to the sky), but still unfortunate. On the plus side, if Apple moves most/all of its chip production to TSMC for its next generation “A” series processor, then that will drive a fairly dramatic increase in revenues, even if the broader market slows.

That being said, TSMC isn’t quite as “safe” as ARM in terms of being levered to the broader industry. If you’re a company like Qualcomm, NVIDIA, or Broadcom, you don’t really have a choice for your instruction set architecture – it’s ARM or bust. While ARM and TSMC do face some threat from Intel (which designs and builds its own chips), that’s really it for competitive pressures for ARM. TSMC on the other hand has to deal with potential competition from Global Foundries and Samsung as foundries (and, to a verylimited extent, Intel). Further, TSMC has to deal with rather extensive capital expenditures that ARM – a vendor of IP – doesn’t have to deal with.

On the other hand, leadership in wafer fabrication pays handsomely. While ARM’s moat is “safe”, TSMC’s raw profitability is in the big leagues – during this quarter alone, the company raked in a cool $1.77B, which is more than ARM takes in as revenue in a year. Of course, for the privilege of these bigger profits (and by extension a bigger company) the risk profile is higher. Everything in business is a trade-off: there are no free lunches.

Can TSMC maintain its leadership?

At 28nm, TSMC was first out of the gate and ended up getting the majority of the business as a result. The question is, will this continue out in time? That’s the multi-billion dollar question. At the 20 nanometer generation, TSMC’s management sees “very little competition” and as a result is likely to own this generation. The question becomes trickier at the 14nm/16nm FinFET nodes.

What the entire foundry industry (both the IBM “fab club” members as well as TSMC) is doing here is taking the 20nm Back End of Line (that is, the portion of IC fabrication where the individual devices such as transistors, resistors, and such) and marrying that to next generation FinFET transistors. What this buys the industry is much higher performance at much lower leakage current levels. In short, this will enable faster chips at the same power or lower power chips at the same performance – the beauty of transistor advances.

Unfortunately, this doesn’t buy anybody any material increases in logic density (SRAM densities will improve). The bad news is that cost/transistor goes up, but the good news is that everyonein the foundry business has to deal with it (except Intel, but I’ll qualify that shortly). I believe that Dr. Chang explained it best on the earnings call,

It is a matter of competition or? We just want to be our cost to be lower than competitors. I mean, this — I come back to the story of 2 people in the camp and a bear, a big bear is approaching. And the first person quickly puts on his running shoes, and the second person says, “What’s the use? The bear is going to out run you anyway; it’s going to run faster than you anyway.” And the first person then starts to run and while he departs, he said to the second person, “All I have to do is to run faster than you, not the bear.” So on this price and costing, all we have to do is to run faster than the competitor.

So, will TSMC outrun Global Foundries and Samsung at the FinFET nodes? My personal expectation is that the answer to this question is “yes” based on prior track records but only time will tell. If it can, then I see no reason for TSMC to not continue to rake in the cash and to keep the lion’s share of the leading edge capacity. But if it can’t then things get more challenging. That being said, there’s another player worth discussing: Intel.

What about Intel?

There’s no denying that as far as transistors go, Intel is usually a generation or two ahead of the foundry players. Today Intel is shipping products built on its 22nm FinFET process and is gearing up to go into production of its first 14 nanometer products in 1Q 2014 – right about when TSMC goes into volume production of its 20 nanometer process. So, on the surface this looks pretty bad – TSMC won’t have FinFETs married to its 20nm BEOL until 1H 2015, while Intel already has a 14nm process in early 2014. But there’s a subtle question that has yet to be answered.

Typically speaking, Intel is much less aggressive about its M1 layer pitch (that is, the minimum metal pitch, which usually determines logic density) than TSMC is at comparably named nodes. For example, at 28nm, TSMC’s M1 pitch was 96nm (actually denser than Samsung’s/Global Foundries’ 114nm pitch, if the Chipworks teardown of the Apple A7 is to be believed) and at 20nm TSMC’s M1 pitch is 64nm. At Intel’s 22nm, M1 pitch is 80nm, but the M1 pitch at 14nm is unknown (since Intel has not yet detailed its process).

If Intel shrinks its M1 pitch from 80nm -> 64nm at its 14nm generation, then the claims that Intel has a density advantage at its 14nm node will be incorrect. However, Intel does claim a 2x density improvement from its 22nm node to its 14nm node. If these claims are accurate, then M1 pitch for Intel’s 14nm process shouldwork out to 56nm (sqrt(2) * 80nm). In this case, Intel would have a logic density advantage of about 30%, all else being equal. But if Intel moves to a 64nm M1 pitch, then Intel’s 14nm process and TSMC’s 16nm process should be roughly equivalent. But let’s take this a step further: what if Intel’s M1 pitch at 14nm is, indeed, tighter than TSMC’s?

The risk isn’t exactly from a foundry perspective. I’m not convinced that Intel wants to play in the general purpose foundry business, particularly as much of TSMC’s leading edge capacity is driven by Intel’s direct competitors. I also am not convinced that Intel is really ready to take meaningful amounts of foundry business from the more established foundry players. After all, there’s a lot of ecosystem work that needs to be done in order to enable this. While I do see Intel taking some steps here, it will be years before we can really view Intel as a competitor.

But the risk isthat Intel’s own products end up superior to those from TSMC’s customers playing in the same space. Now, there’s more to what makes a product better/worse than what transistor technology it was built on (designs matter, too), but transistors are fundamental.

What’s the bottom line?

The bottom line is that TSMC is a very high quality company that has done everything right and will likely consistently outperform the broader semiconductor industry for years to come. It has ramped up its R&D to be very competitive on the actual process development. While the other foundry players will try to play catch-up, TSMC’s revenue and profitability advantages against its peers is staggering, which positively feeds back into TSMC’s R&D and drives continued leadership. While there’s risk that Samsung and Global Foundries “catch up” at the next generation nodes, I’ll have to see it to believe it, and even then being there with technology doesn’t mean that all of TSMC’s ecosystem and design enablement work is worth nothing – it’s still a competitive advantage that can (and likely will) be capitalized on.

TSMC’s shares rose about 2% in trading following the release of its earnings report, and while I don’t have a crystal ball, I do expect TSMC to continue to out-perform the semiconductor industry as a whole and expect the shares to trade much higher over the coming years.

More articles by Ashraf Eassa…

Also Read: TSMC CEO Succession Plan

October 13, 2013December 19, 2023

The TSMC CEO Succession Plan!

The TSMC CEO Succession Plan!
by Daniel Nenni on 10-13-2013 at 8:00 pm
Categories: Foundries, TSMC

The foundry executive shuffle continues at Samsung, GlobalFoundries, and TSMC. Some expected, some not, the needs of the many outweigh the needs of the few. As I have mentioned before I have no inside knowledge as to who will be named as Dr. Morris Chang’s successor but here is my candidate for the next TSMC CEO.

First, the executive shuffle: Mike Noonen is no longer Executive Vice President, Global Products, Design, Sales & Marketing at GlobalFoundries. This came as a shock to me as the changes I witnessed during his tenure were amazing. Hopefully Mike will take a CEO position in EDA or IP and continue with the transformation of the semiconductor industry. John McClure also left GlobalFoundries, John was Mike’s #2 guy. John is now with Intel’s Mobile Communications group. In fact, Intel has hired quite a few GF people so they are definitely serious about the foundry business.

Second: Ana Hunter is no longer Foundry Vice President at Samsung after more than seven years, which, by the way, is how long Samsung has been in the foundry business. Look for Samsung to be the #2 foundry when 14nm revenue kicks in and you can thank Ana for that, absolutely. Ana now works for GlobalFoundries.

Third: Dr. Shang-yi Chiang will retire at the end of October. Shang-Yi is TSMC’s Executive Vice President and Co-Chief Operating Officer. He retired from TSMC as Senior Vice President of R&D in July 2006 and returned in September 2009 so I would not be surprised if Shang-Yi comes back to TSMC after a much deserved break.

If you look at the TSMC corporate executives page you will see many people that are qualified to succeed Dr. Morris Chang. Dr. Mark Liu, Co-Chief Operating Officer, is the odds on favorite. Prior to joining TSMC, from 1987 to 1993, he was with AT&T Bell Laboratory. From 1983 to 1987, he was a process integration manager of CMOS technology development at Intel Corporation, Santa Clara, CA, developing silicon process technologies for Intel microprocessor. Mark has a PhD in EE and CS from UC Berkeley.

While Mark is the logical choice he is not who I would choose. Dr. Cliff Hou would be my choice as the new TSMC CEO, absolutely.

Dr. Cliff Hou was appointed TSMC’s Vice President of Research and Development (R&D) in 2011. He joined TSMC in 1997 and was previously Senior Director at Design and Technology Platform where he established the Company’s technology design kit and reference flow development organizations. He also led TSMC in-house IP development teams from 2008 to 2010. Cliff has 20 U.S. Patents and serves as a board member of Global Unichip Corp. He received a Ph.D. in electrical and computer engineering from Syracuse University.

Why Dr. Cliff Hou you ask? Cliff knows design enablement and is trusted by the top fabless semiconductor companies around the world, that’s why. Moving forward TSMC’s greatest challenge is not technical, which I’m sorry to say since that is their strong suit. TSMC’s greatest challenge is political. Their next challenge is retaining the commanding market share that 28nm brought them.

As the semiconductor industry continues to transform, TSMC and the other foundries must continue to integrate with their customers. Paul McLellan and I recently finished a book “Fabless: The Transformation of the Semiconductor Industry” and the research we did was enlightening. Historically speaking, the semiconductor industry transformed from the transistor to the IC to IDMs to the ASIC to the FPGA to fab-lite to fabless. The transition continues as fabless semiconductor companies consolidate and become more integrated with the foundries. GlobalFoundries calls this Foundry 2.0. TSMC calls this the Grand Alliance. I call this the natural course of business in Silicon Valley.

Bottom line: When 90% of the semiconductor wafers are purchased by 10% of the companies you really need to accommodate that 10%. Detractors will say that Dr. Cliff Hou does not have enough gray hair to be CEO. I do not agree. Cliff Hou is the same age as the people who buy the commanding share of the wafers and they buy from people who they know and trust.

October 4, 2013June 14, 2019

TSMC OIP 2013 Trip Report!

TSMC OIP 2013 Trip Report!
by Daniel Nenni on 10-04-2013 at 4:00 pm
Categories: Foundries, TSMC

The 5[SUP]th[/SUP] annual TSMC OIP Forum was last week and thankfully there were no surprises with the exception of how many people asked me who I think will be the next TSMC CEO. Certainly I have no idea but I would be happy to use my incredible powers of deductive reasoning to determine who it will be.

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem.

First the conference, as I have written before 20nm is ramping, exceeding expectations. We will see production 20nm FPGAs and mobile devices in Q1 2014, absolutely. This comes not only from TSMC’s Jack Sun and Cliff Hou, but also from the fabless crowd: Bob Maines of Oracle, Brad Howe of Altera, VJ Janapaty of LSI Logic, Esin Torfioglu of QCOM, and Sandeep Bharathi of Xilinx. Always listen to the crowd, never listen to the press, especially EETimes.

It is very sad to see EETimes go the tabloid journalism route of late. As you can see their Alexa ratings are dropping as people chose to read articles about semiconductors written by people who actually work in the semiconductor industry:

EETimes
2012 Rank: 24,870
2013 Rank: 26,573

Bounce Rate 65.30%
Daily Pageviews per Visitor 1.82
Daily Time on Site 2:09

SemiWiki
2012 Rank: 431,594
2013 Rank: 183,805

Bounce Rate 42.20%
Daily Pageviews per Visitor 6.10
Daily Time on Site 10:28

DeepChip
2012 Rank: 1,175,172
2013 Rank: 1,736,007

Bounce Rate 70.80%
Daily Pageviews per Visitor 1.70
Daily Time on Site 2:33

As I have mentioned before, 20nm will be a short node as the mobile companies will quickly transition to FinFETs making 28nm one of the longest and most profitable nodes we will ever see. 28nm ramped much faster than 40nm and I expect 20nm to be a quick ramp as well with iProducts shipping a butt load of 20nm SoCs in Q4 2014. TSMC will own 20nm as it did 28nm, but again, it will be a short node.

Also Read: TSMC Awards Berkeley Design Automation

16nm is also on track. Cliff went into significant detail about the status of 16nm PDKs and IP leaving little doubt that we will be ready to tape-out this quarter. Cliff also gave a status of CoWos (resounding success) and 10nm was again committed for 2015 but it really is too soon to say for sure. One thing I do know is that 10nm will not involve EUV and will require triple patterning.

According to the Silicon Valley crowd, Samsung and TSMC are both getting FinFET tape-outs this quarter. TSMC is a little behind Samsung in releasing the 1.0 PDK but Samsung’s 1.0 PDK is having correlation issues so this race will be a photo finish. This type of competition is what keeps us fabless folks strong, absolutely.

One other thing I wanted to mention before I go back into the trenches; there is a TSMC article on Seeking Alpha that is definitely worth a read:

Taiwan Semiconductor Looks Undervalued Ahead Of Key Drivers

Paul McLellan and I met the author at IDF last month and had a somewhat heated discussion on the importance of the fabless semiconductor ecosystem. I provided him with an advance copy of our book “Fabless: The Transformation of the Semiconductor Industry” and after many discussions and focused research he now has a much better understanding of what we do. Expect more ecosystem related articles from him on SemiWiki in the coming weeks.

Ah, no room for my TSMC CEO transition analysis. It turned out to be quite lengthy, a blog in itself, so I will post it next weekend if you all are still interested.

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September 28, 2013June 14, 2019

TSMC Open Innovation Platform Forum, October 1st

TSMC Open Innovation Platform Forum, October 1st
by Paul McLellan on 09-28-2013 at 5:00 am
Categories: EDA, Foundries, IP, TSMC

One of TSMC’s two big Silicon Valley events each year is the Open Innovation Platform (OIP) Forum. This year it is on Tuesday October 1st. It is in the San Jose Convention Center and starts at 9am (registration opens at 8am). Pre-registration to attend is now open here or click on the image to the right.

From 9.10 to 9.40 is the TSMC keynote and then from 9.40 to 10.10 is a presentation on TSMC and its Ecosystem for Innovation.

After a coffee break, the rest of the day is in three parallel tracks: EDA, IP and a services track that also contains little leavening of EDA and IP too. The big guns are all there: Cadence, Synopsys, Mentor and ARM are all presenting. Smaller companies such as iRocTech and Sidense are also there. The complete program is below.

[TABLE] cellpadding=”4″ style=”width: 97%”
|-
| align=”center” style=”width: 15%” | [TABLE] cellpadding=”10″ style=”width: 100%”
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| align=”center” |
|-

|-
| 11:00 – 11:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Design Reliability with Calibre Smart-Fill and PERC
|-
| valign=”top” align=”center” | Broadcom & Mentor Graphics
|-

|-
| 11:30 – 12:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | TSMC 16nm FinFET SRAM Design Verification
|-
| valign=”top” align=”center” | Synopsys
|-

| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | Soft-Error Testing at Advanced Technology Nodes
|-
| valign=”top” align=”center” | GUC
|-

|-
| 12:00 – 13:00
| colspan=”3″ valign=”top” align=”center” | Lunch
|-
| 13:00 – 13:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | Addressing Custom Design Challenges for IP Design at 16nm FinFET technology
|-
| valign=”top” align=”center” | Cadence
|-

| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| valign=”top” align=”center” | Optimizing Cortex-A57 for TSMC 16nm FinFET
|-
| valign=”top” align=”center” | ARM
|-

|-
| 13:30 – 14:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | A Synergetic, Multi-Partner, Soft Error Rate Analysis Framework For Latest Process Nodes
|-
| valign=”top” align=”center” | iROC
|-

|-
| 14:00 – 14:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | EDA-Based DFT for 3D-IC Applications
|-
| valign=”top” align=”center” | Mentor Graphics
|-

|-
| 14:30 – 15:00
| colspan=”3″ align=”center” | Coffee Break
|-
| 15:00 – 15:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Advanced Power, Signal and Reliability Verification for 20nm, 16nm FinFET, and 3D-IC Designs
|-
| valign=”top” align=”center” | ANSYS Apache
|-

| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | ARM POP IP Accelerating Time-to-PPA in Mainstream Mobile
|-
| valign=”top” align=”center” | ARM
|-

|-
| 15:30 – 16:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Low Power and Faster Timing ECO for sub-20nm Designs
|-
| valign=”top” align=”center” | Dorado Design Automation
|-

|-
| 16:00 – 16:30
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | FinFET modeling and extraction solution for TSMC’s advanced 16-nm process
|-
| valign=”top” align=”center” | Synopsys
|-

|-
| 16:30 – 17:00
| valign=”top” align=”center” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| valign=”top” align=”center” | Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC
|-
| valign=”top” align=”center” | Mentor Graphics & nVIDIA
|-

|-
| 17:00 – 18:00
| colspan=”3″ align=”center” | Networking and Social Hour
|-

TSMC created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served more than 600 customers, manufacturing more than 11,000 products for various applications covering a variety of computer, communications and consumer electronics market segments. Total capacity of the manufacturing facilities managed by TSMC, including subsidiaries and joint ventures, reached 15.1 million eight-inch equivalent wafers in 2012. TSMC operates three advanced 12-inch wafer GIGAFAB™ facilities (fab 12, 14 and 15), four eight-inch wafer fabs (fab 3, 5, 6, and 8), and one six-inch wafer fab (fab 2). TSMC also manages two eight-inch fabs at wholly owned subsidiaries: WaferTech in the United States and TSMC China Company Limited, In addition, TSMC obtains 8-inch wafer capacity from other companies in which the Company has an equity interest.

TSMC’s 2012 total sales revenue reached a new high at US$17.1 billion. TSMC is headquartered in the Hsinchu Science Park, Taiwan, and has account management and engineering service offices in China, Europe, India, Japan, North America, and, South Korea.

September 18, 2013June 14, 2019

A Brief History of TSMC’s OIP part 2

A Brief History of TSMC’s OIP part 2
by Paul McLellan on 09-18-2013 at 11:00 pm
Categories: Foundries, TSMC

The existence of TSMC’s Open Innovation Platform (OIP) program further sped up disaggregation of the semiconductor supply chain. Partly, this was enabled by the existence of a healthy EDA industry and an increasingly healthy IP industry. As chip designs had grown more complex and entered the system-on-chip (SoC) era, the amount of IP on each chip was beyond the capability or the desire of each design group to create. But, especially in a new process, EDA and IP qualification was a problem.