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TSMC and Apple Aftermath

TSMC and Apple Aftermath
by Robert Maire on 01-21-2019 at 7:00 am
Categories: Foundries, Semiconductor Advisors, Semiconductor Services, TSMC
9 Comments

TSMC reported an in line quarter, as expected and also reported down Q1 guidance, also as expected. The only thing some investors may have been caught off guard about is the magnitude of the expected drop, 14%, from $9.4B to $7.35B. This is the largest quarter over quarter drop for TSMC in a very long time. Importantly for TSMC, 7NM was 23% of business, so leading edge remains very solid and 20NM and below was half of all business.

CAPEX is being cut, as we had projected, by several hundred million dollars, probably at least 5% and the cuts may get deeper as time goes along. We expect most of the cuts to be in H1 2019 with H2 2019 left open to see how business recovers.

We have been very clear about the CAPEX cuts and “trickle down” impact from Apple. We were interviewed on Bloomberg TV 10 days ago regarding Apple and had specifically called out TSMC as the most impacted and the overall capex cuts;

Link to Bloomberg TV interview on Apple, TSMC & CAPEX

For any one who was paying attention over the last year this slow down should come as no surprise. We don’t expect a large downtick in the stocks as the news should be well expected. It is, none the less, another slug of bad news, in what we expect to be an earnings season of a flow of negative news bites. We think it will be hard to escape the negative flow and likely further downward number revisions.

To be clear we still love TSMC and think they are the greatest foundry ever and right now, the most advanced chip maker. However if demand sucks theres not a lot you can do about it, no matter how good you are. Apple is 20% of TSMC’s business and chips for mobile are obviously well beyond that so the impact on TSMC will be significant and it will take a while to work out.

Channel Chokes
The other large problem to keep our eye on is how bloated the channel is given the smart phone slowdown. Our checks indicate there is a lot of unsold product in the pipeline that will take time to work out. A lot of the inventory is likely held as unpackaged wafers, held at lower unfinished goods pricing but represents a lot of chips when they get packaged. This hidden inventory is likely high and will take several quarters or more to work off and even longer while demand is depressed so we wouldn’t be holding our breath for a quick bounce back.

Chip equipment companies are likely to be even more negative given that one of their largest and clearly most advanced customers has put the brakes on. While bleeding edge business is likely the least impacted we could still see projects and shipments delayed and pushed out from one quarter into the next as TSMC modulates spending to support their profitability. One thing the industry has become good as is quick adjustments to near term trends and they can put the brakes on quickly. This is one of the supporting reasons for our concern about another down leg for the industry.

AMAT most negatively impacted
If Lam is the house that memory built then AMAT is the house that foundry built. AMAT has had a long and deep partnership with TSMC as their main supplier. To a lesser extent, KLAC and ASML could see some further weakness out of TSMC.

Consumable companies not so defensive as believed
The common wisdom is that consumable companies such as ENTG, CCMP and others who are wafer start driven are more of a “Steady Eddy” type of business , compared to capital equipment providers, except when wafer starts experience the sharpest drop in over ten years as is the case here. Its clear that even the consumable suppliers will get hit as wafer starts slow and inventory of built wafers gets worked off.

The stocks
We don’t expect that much of a negative reaction as much of the negative news has already been baked in a while ago. In addition the stocks seem to be building up a downside resistance to all the negative news. We could see individual stocks sell off as they adjust their numbers downward on their respective conference calls as the trickle down continues.

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Samsung vs TSMC 7nm Update

Samsung vs TSMC 7nm Update
by Daniel Nenni on 01-02-2019 at 7:00 am
Categories: Foundries, Samsung Foundry, TSMC
4 Comments

The semiconductor foundry business has gone through a dynamic transformation over the last 30 years. In the beginning the foundries were several process nodes behind the IDMs with little hope of catching up. Today the foundries are leading the process development race at 10nm – 7nm, and will continue to do so, absolutely.

If you look at the foundry landscape, TSMC has the advantage because they are TSMC, the trusted foundry partner with the most mature and complete ecosystem bar none. TSMC is also a process technology leader and fierce competitor.

The market for Samsung Foundry as I see it is three-fold:

  • They are not TSMC. Capacity is not an issue with Samsung and it is always good to have foundry options. TSMC and Samsung are the only two leading edge foundries left so this is a much bigger point than most imagine.
  • Technology. Leading edge fabless companies look for the best technology that will also meet their time to market requirements. Samsung was ahead of TSMC at 14nm and they did quite well at that node. At 10nm and 7nm Samsung was a bit behind TSMC but Samsung 7nm had EUV before TSMC so some fabless companies are now leading with Samsung.
  • Pricing. Samsung has the best wafer pricing the industry has ever seen. Being the largest memory manufacturer does have its advantages and wafer pricing is one of them.To catch up with the latest on foundry process technology I talked to Scotten Jones, internationally recognized semiconductor expert and founder of IC Knowledge, a technology consulting company that models the economics of semiconductors. Scott has been writing for SemiWiki since 2014, his blogs are on the IC Knowledge landing page. Here are Scott’s latest thoughts on TSMC versus Samsung at 7nm:
    • Contacted Poly Pitch (CPP) – both TSMC and Samsung claim a CPP of 54nm for 7nm but for both of them I believe their actual CPP for cells is 57nm.
    • Metal 2 pitch (M2P) – Samsung is 36nm and TSMC is 40nm.
    • Tracks – Samsung minimum cell track height is 6.75 and TSMC is 6.0.
    • Diffusion break – TSMC optical process (7FF) is double diffusion break (DDB) and they are reported to be going to single diffusion break (SDB) for their EUV process (7FFP). Samsung 7nm has a 1[SUP]st[/SUP] generation process (I believe this is 7LPE) and it is DDB, they also have a second generation process (I believe this is 7LPP) that is also DDB. At VLSIT this year they talked about a 3[SUP]rd[/SUP] generation process with SDB. It is hard to know what this really is, at 10nm their second generation process was actually their 8nm process so this could be their 5nm process or it could really be a third generation 7nm process.
    • Transistor density – the minimum cell logic density for TSMC 7FF is slightly better than Samsung 7LPE or 7LPP. TSMC EUV 7FFP is slightly better than Samsung “3[SUP]rd[/SUP] generation” 7nm.
    • SRAM cell size – I think the SRAM cell size is the same for all three Samsung generations (I have a number for the 3[SUP]rd[/SUP] generation process) and both TSMC generations (I have a number for 7FF) but I am not positive. Samsung has a slightly smaller SRAM cell.

    According to Scott, overall, the two processes are similar in density with TSMC leading in the ramp-up and likely yield and I agree, absolutely.

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Essential Analog IP for 7nm and 5nm at TSMC OIP

Essential Analog IP for 7nm and 5nm at TSMC OIP
by Tom Simon on 10-24-2018 at 7:00 am
Categories: Events, Foundries, IP, Silicon Creations, TSMC

When TSMC’s annual Open Innovation Platform Exposition takes place, you know it will be time to hear about designs starting on the most advanced nodes. This year we were hearing about 7nm and 5nm. These newer nodes present even more challenges than previous nodes due to many factors. Regardless of what kind of design you are undertaking at these nodes, clocking IP is essential. This IP is analog and has even trickier design constraints at these smaller nodes. Andrew Cole at Silicon Creations gave a presentation at the Exposition that provide a lot of insight into what is required to produce this important foundation IP.

Silicon Creations has delivered clocking IP, such as PLLs, that have been used literally billions of times on production chips. Achieving success on this many instances requires tremendous verification resources. One of the interesting parts of Andrew’s presentation discussed the size of their server farm that are used for AFS simulation. They have two sites with more than 2000 cores. The combined RAM is 15TB. They need over 2000 AFS licenses to run their SPICE simulations. Being analog guys, they have even added their own liquid cooling on the processors so they can overclock them.

So why the need for such enormous resources? Andrew started by mentioning the application target for many of these ICs, which turns out to be IoT. He admitted that it is an over used term and has no good definition. However, it’s a useful shorthand for ICs that need to operate on low power, can start and stop quickly, have low leakage, and require few or no external components. Silicon Creations leverage TSMC’s low power processes: 180LP, 40ULP, 22ULL and FinFETs from 16nm to 5nm. These PLLs consume as little as 5uW and can start in as little as 3 clock cycles.

Andrew talked about how analog designs scale as processes shrink. They have seen their PLLs become about 8x smaller in the move from 180nm to 5nm. The limiting factor is noise which turns out to be proportional to kT/C. As such, capacitor values play a big role in determining noise. The other big challenge is wire resistance. With the significant relative increase in wire resistance, it is no longer possible to use lumped R for simulation. Silicon Creations has moved to performing simulation using fully distributed netlists for R and C. Add to this the need to use fully 3D aware tools, and the problem grows substantially. For an example PLL, it now takes 100 times longer to run post layout simulation for 5nm than it did at 40nm.

PLLs and SerDes face even more simulation obstacles. Their jitter requirements are on the order of 0.1ps. Clock cycles are ~100ps. System level activity can stretch out to 1ms, which is 10 orders of magnitude greater than the resolution needed to see jitter issues. Next, factor in the need to run Monte Carlo transient simulations to ensure good yield and it’s easy to see why Silicon Creations has had to scale up their server farm so extensively.

The next question is how well does all this simulation effort correlate to silicon. The answer is: quite well. For power, the mean and standard deviation match closely – sim: 3.02uA 1.5% to meas 3.15uA 1.6%. Below are the PLL fast locking plots.

Lastly, here is the graph for phase noise.

Few IP companies have as much experience and as many instances in the field as Silicon Creations. For digital design teams eager to take advantage of the benefits of 5nm, using proven and well designed and verified IP for clocking, Silicon Creations offers a compelling solution. Their 5nm solutions are taping out shortly. More information on the topic of advanced node analog clocking IP is available on the Silicon Creations website.

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TSMC Q3 2018 Earnings Call Discussion!

TSMC Q3 2018 Earnings Call Discussion!
by Daniel Nenni on 10-22-2018 at 7:00 am
Categories: Events, Foundries, TSMC
8 Comments

The TSMC OIP Forum was very upbeat this year and now we know why. It wasn’t long ago that some media outlets and a competitor said 7nm would not be a popular node because it is too expensive blah blah blah. People inside the fabless semiconductor ecosystem however know otherwise. As I have said before, 7nm will be another strong node for TSMC, déjà vu of 28nm. The difference being that there will not be cloned 7nm processes like 28nm so TSMC market share and margins will remain strong, my opinion.

Let’s take a look at the Q3 2018 earnings call transcript and see what else we can learn:

Now let’s take a look at revenue by technology. 7-nanometer process technology contributed 11% of total wafer revenue in the third quarter. 10-nanometer accounted for 6%, while the combined revenue from the 16- and 20-nanometer accounted for 25%. Advanced technologies, defined as 28-nanometer and more advanced technologies, accounted for 61% of the total wafer revenue.

Apple is > 17% of Q3 revenue if you include 20nm (iPhone 6) and 16nm (iPhone 6+ and iPhone 7) legacy products.

Now let me make some comment about capacity and CapEx. At TSMC, we build our capacity according to the customer demand. We are continuing to increase 7-nanometer capacity to meet the strong customer demand. We reiterate our 2018 CapEx to be between US$10 billion and US$10.5 billion. In addition, as I have talked about before, although our leading edges capital cost continue to increase due to increasing process complexity, we are able to offset its impact to our CapEx by productivity improvements and further optimization of our capacity planning.

CAPEX can be further reduced by purchasing the equipment GF has in NY? TSMC will move from 5 layer EUV at 7N+ to 14 layer EUV at 5nm so they will need those extra ASML EUV Systems. TSMC will build new fabs for 5nm. In my opinion 5nm will be another big node for TSMC so I expect CAPEX spending to be at the high end for sure.

TSMC CEO C.C. Wei is a very strong leader and from what I am told he is loved by TSMC employees so I expect a very good run under his command. As we know from Intel’s latest debacle, a great CEO is key and C.C. is a great CEO, absolutely. He also has a sharp wit and is approachable and engaging which strengthens his credibility.

Now let me update you about the August 3 virus incident. On August 3, TSMC experienced a computer virus outbreak, which affected a number of computer systems and fab tools. The infection was due to misoperation and insufficient firewall controls. We have since corrected this problem to ensure such viruses will not happen again in the future. Our remediate actions including the following: implementing an automated system to guarantee fool proof execution so that such misoperation will not happen again; enhanced firewall control for fab isolation; and network control to each individual computer. More enhancements now are ongoing, too, for further improve tool immunity against future infections. TSMC sets top priority for such security enhancement.

From what I was told it was a vendor’s fault, but I am glad to see TSMC assume full responsibility and take the appropriate actions. I’m not a big fan of finger pointing as it is a sign of weak leadership.

Now let me talk about the N7 and N7+ and the EUV’s progress. TSMC’s N7 technology is now available for customers to unleash their innovations. This is the first time in the semiconductor industry the most advanced logic technology is available for all product innovations at the same time. We continue to work with many customers on N7, N7+ product design and expect to see more than 100 customer product tape-outs by end of 2019. We expect 7-nanometer to be a long node and will attract multiple waves of customer adoptions.

Absolutely.

N7+ is in risk production now. Since the N7+ has 15% to 20% better density and more than 10% lower power consumption, we are working with many customers for their second wave product designs in N7+. Although the number of tape-outs today account for a small portion of the total 7-nanometer tape-outs, we expect the activity to pick up at a rapid pace in 2020 and beyond. Because the N7+ is using a few layers of EUV photolithography to have better cycle time and patent control, we have made steady progress on EUV technology development towards high-volume production. Tool availability, EUV power, productivity, defect reduction, mask improvement, material and process optimization are all on schedule. A few customers have already made plans to adopt our N7+ in their 2019 products.

N7+ really is a test bed for EUV. They are doing 5 layers in preparation for a full EUV implementation of 14 layers at 5nm. It should not be hard to figure out the N7+ customers as they are the early adopters of 5nm. This half node approach has worked well since 20nm (Apple coming to TSMC) so I expect it to continue.

Let me move to our N5 status. Our N5 technology development is on schedule. We have completed the design solution development and are ready for customers’ design start. The N5 risk production schedule in first half 2019 stays the same. Compared to N7, TSMC’s N5 deliver 1.8x to 1.86x logic area reduction and close to 15% to 18% speed gain and ARM A72 core. We expect to receive first customer product tape-out in spring of 2019, followed by production ramp in first half 2020.

Apple will use 5nm in 2020 so you can bet it will be in HVM in the first half of 2020. From what I hear 5nm test chips are meeting/exceeding expectations and the PDK is solid so I see no reason to doubt TSMC’s 5nm schedule at this time.

Now let me talk about advanced packaging update. TSMC has been developing advanced wafer-level packaging technologies to integrated advanced SoCs, memories, integrated passive device, to enhance system performance. We believe our advanced packaging solutions will contribute to our business growth. We are now expanding the applications of both CoWoS and InFO especially for high-performance computing. Most of the CoWoS products require integration of SoC with High Bandwidth Memory, HBM, in 3D stack. We are making good progress in qualifying multiple HBM sources through close collaboration with customers and the DRAM suppliers. We are also working with a few leading customer on SoIC, which stands for system on integrated chips, where multiple heterogeneous chipsets will be integrated with close proximity to deliver better performance. And we target to start production in 2021 time frame.

TSMC has really done a nice job on packaging. I remember when CoWos came out there were quite a few doubters. Visionaries like myself and Herb Reiter saw this coming but even we are surprised at the amount of resources TSMC has committed to packaging and the excellent results. TSMC now has the MOST sticky foundry process in the world.

Now to the Q&A. Sometimes there are some very funny interactions but this is not one of them:

Michael Chou Deutsche Bank AG, Research Division – Semiconductor Analyst Is it fair to say that 7-nanometer sales portion will be more than 20% of total sales for the whole year next year?

Lora Ho Taiwan Semiconductor Manufacturing Company Limited – CFO and Senior VP of Finance Let me answer that. You have seen our report. The third quarter 7-nanometer accounts for 11%. The fourth quarter will be more than 20%. So for whole year 2018, 7-nanometer will contribute close to 10% of total TSMC revenue. Go beyond 7 — 2018, and we will have very, very strong ramp, in 2019 as well, we expect the revenue contribution will be much higher than 20%.

Randy Abrams Crédit Suisse AG, Research Division – MD and Head of Taiwan Research in the Equity Research Department Okay. The second question I wanted to ask was about the 7+ versus 5-nanometer. You mentioned 2020 would see the very strong ramp-up of tape-out and activity in volume on 7+. Is it your view — I think last conference, Mark said 5 was a little bit more conservative at this stage. So how’s your view now for interest activity and expectation for a steep ramp-up of 5 into 2020?

C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – CEO & Vice Chairman We still expect very fast ramp on 5. The reason is simple. Because of a lot of products developed in the AI area, you need the speed, you need the lower power, and you also need a small footprint. So from this — from today, we can see when we work with our customers, the ramp will be steep again.

Roland Shu Citigroup Inc, Research Division – Director and Head of Regional Semiconductor Research Okay. Can you just reiterate the growth breakdown for this 4 platforms next year?

C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – CEO & Vice Chairman Okay, let me give you some color on it. In the next few years, if we look at ahead, actually, the smartphone is going to be in our daily life even more and more. So we have a 4 growth engine: one is a mobile phone, actually it’s a high-end smartphone; second one is a high-performance computing; automotive; IoT. The mobile phone probably for TSMC will have a 5 year CAGR, if I look at it right from today, it will be mid-single digit growth. And the all others 3 platorms will have a very comfortably double-digit growth in the 5 year time frame.

Bill Lu UBS Investment Bank, Research Division – MD and Asia Semiconductors Analyst Great. I know 2018 is not over yet, but if you think about the next couple of years, I know TSMC has talked about a long-term growth rate of 5% to 10%. Now I feel like more recently, you’ve talked a lot more about the progress on 7-nanometers. We all know about Intel’s struggles with their process technology. And it’s public information. They’ve announced it, right? So — and then you’ve got some good design wins. Can you talk about your long-term outlook in 2019? Given these drivers you just said, out of the — 3 out of the 4 new drivers will be above 10%. So are we looking at something more towards the high end of that? Or how do you think about that?

C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – CEO & Vice Chairman We continue to say 5% to 10% growth rate. Probably I would like to — following your question, I would like to say probably tends to be at the higher side of that 5% to 10%.

C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – CEO & Vice Chairman Okay, actually the question is about the EUV and how much of the benefit we can get from the EUV, right? Usually, if we are not using the EUV, sometimes for the very critical dimension on the N7, you have to — or N7+, you have to use the 4 layers of lithography to pattern one of the critical dimension. Now using the EUV, you’re just using 1 layer so that you reduce the cycle time by 4x of photolithography, 4x of etch. Now you become 1 lithography, 1 etch. In total, how many layers we reduced? That depends on the customer’s requirement, but usually I just give you a hint already, right, 4 layer can become 1 and we are replacing some of the 3 layers to become 1 and we have a few layers of that. So that give you a hint. Cycle time reduction, definitely, because you do 4x into 1x, that’s a big advantage. Productivity-wise, today, EUV is progress very well — up to our expectation. And in fact, TSMC has turned on the 250-watt power and we believe we are the only one company continuously run the 250 watts EUV power so far today.

From what I hear ASML has 500-watt power working in the lab so 5nm EUV throughput should not be a problem. The question I have, now that EUV is in production, will ASML actually make money on EUV? After the many years of R&D and EUV broken promises? Billions of dollars must have been spent…

C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – CEO & Vice Chairman Okay. Actually, I don’t want to comment on my competitors’ strategy. But let me, again, stress our mature nodes’ strategy. We continue to develop some of the specialty technology to meet the customers’ requirement, right, I just stated in that. And yes, a lot of specialty technology we are doing, I give you some example already, power management IC, CMOS, MEMS, everything. So that will help us to compete with our competitor. Actually, this kind of specialty technology particularly we have to work with the customer. And so that’s why I say working with the customer to meet their requirement. And that, in turn, to keep TSMC’s business. And that’s a way that we migrate the logic technology — pure logic technology to the more advanced node. But for the existing capacity, we develop into the specialty technology. And so our strategy is still meet customer’s requirement, but we don’t increase the existing logic capacity.

C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – CEO & Vice Chairman I think the AI’s application would be everywhere, actually, from the edge server or to the end device that’s just like the smartphone of everybody. So this kind of a development is to our advantage because TSMC certainly have a technology leadership. In order the AI would be effective, you need a very advanced technology for the highest performance computing. So I don’t see the effect that you are talking about, this application is better than that so that affected the growth or something. No, it will be continues to grow. And I expect this growth much faster than I predicted here.

This is what I have been saying, AI everywhere. And with AI you get increased demand for performance, low power, and increased density which leads to increased leading edge process technology demand. This is really good news for TSMC and the fabless semiconductor ecosystem of course.

These are the questions that interested me. You can see the rest HERE. There is a lot more to discuss so let’s do that in the comments section.

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Top 10 Highlights from the TSMC Open Innovation Platform Ecosystem Forum

Top 10 Highlights from the TSMC Open Innovation Platform Ecosystem Forum
by Tom Dillinger on 10-09-2018 at 7:00 am
Categories: Events, FinFET, Foundries, TSMC
2 Comments

Each year, TSMC hosts two major events for customers – the Technology Symposium in the spring, and the Open Innovation Platform Ecosystem Forum in the fall. The Technology Symposium provides updates from TSMC on:
 Continue reading “Top 10 Highlights from the TSMC Open Innovation Platform Ecosystem Forum”

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TSMC and Synopsys are in the Cloud!

TSMC and Synopsys are in the Cloud!
by Daniel Nenni on 10-08-2018 at 7:00 am
Categories: EDA, Synopsys, TSMC
3 Comments

EDA has been flirting with the cloud unsuccessfully for many years now and it really comes down to a familiar question: Who can afford to spend billions of dollars on data center security? Which is similar to the question that started the fabless transformation: Who can afford to spend billions of dollars on semiconductor manufacturing technology?

TSMC has partnered with cloud vendors Microsoft and Amazon to bring EDA into the 21st century. I have said it before, if anybody could do it TSMC could, which makes TSMC all that more sticky as a pure-play foundry. What other foundries have the ecosystem and trust of the semiconductor industry to do this?

The one issue that is still in process is the software business model. From what I am told EDA software licensing has not changed to a traditional pay-per-use cloud model yet. It really is uncharted territory so let’s look at how we got EDA licensing to where it is today.

We started with perpetual licenses that were locked to a specific machine (not good for EDA). Next was the WAN licensing that would let a perpetual license float around using a license server (good), followed by the flexible access model (FAM) which was a three year all-you-can-eat approach offered by a specific vendor (horribly not good). The software subscription licensing that we use today came next where you lease a software license for three years (very good). One company added a remix clause that allowed customers to change the license counts from one product to another (not good). The EDA company that I previously worked for added weekly tokens that can be used for peak simulation/verification times (very good). The token model worked quite well and added much more total revenue than previously thought and gave chip designers more time simulating and verifying. I feel that the pay-per-use cloud pricing would have a similar result, additional revenue above and beyond annual EDA budgets and better chips, absolutely.

The other thing that I want to point out is how important your relationship with the foundry is. I have made a career of it, helping emerging EDA and IP companies work with the foundries creating revenue streams inside the foundry and outside with the top foundry customers. It is interesting to note that Cadence and Synopsys are the two EDA partners TSMC chose to start with. I’m sure the others will follow but take note, Synopsys, the number one EDA and IP company, does not offer their own cloud, they are all-in with TSMC.

One of the keynotes at the TSMC OIP conference last week was Kushagra Vaid, GM and distinguished Engineer at Microsoft Azure (cloud). Before joining Microsoft in 2007 he spent 11+ years designing microprocessors at Intel. It is always nice to talk semiconductor design with someone who actually designed semiconductors. I spoke with Kushagra and Suk Lee after lunch and am convinced that, after numerous failed attempts, EDA is finally in the cloud and will stay there, my opinion.

“Microsoft Azure is pleased to be a TSMC premier partner in the OIP Cloud Alliance, and we’re honored to receive a 2018 partner of the year award from TSMC for our joint development of theVDE cloud solution,” said Kushagra Vaid, GM and Distinguished Engineer, Azure Hardware Infrastructure, Microsoft Corp. “Our collaboration with TSMC will help usher in modern silicon development that leverages the capabilities of the Azure cloud platform.”

“Synopsys has been a TSMC OIP Alliance member for EDA flows and IP for 11 years, and we have expanded our partnership with TSMC to enable IC design in the cloud,” said Deirdre Hanford, co-general manager, Synopsys Design Group. “We have collaborated with Amazon Web Services and Microsoft Azure to provide a secure and streamlined flow for TSMC VDE. The Synopsys Cloud Solution has passed the rigorous TSMC security and performance audits and is ready for our mutual customers to design in the cloud with TSMC collateral using Synopsys tools and IP.”

Synopsys Announces Availability of TSMC-certified IC Design Environment in the Cloud

TSMC Recognizes Synopsys with Four Partner Awards at the Open Innovation Platform Forum

Synopsys Design Platform Enabled for TSMC’s Multi-die 3D-IC Advanced Packaging Technologies

Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC N7+ FinFET Process

Synopsys Digital and Custom Design Platforms Certified on TSMC 5-nm EUV-based Process Technology

Synopsys Delivers Automotive-Grade IP in TSMC 7-nm Process for ADAS Designs

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Custom SoC Platform Solutions for AI Applications at the TSMC OIP

Custom SoC Platform Solutions for AI Applications at the TSMC OIP
by Daniel Nenni on 09-27-2018 at 12:00 pm
Categories: Events, FinFET, Open-Silicon, Semiconductor Services, TSMC

The TSMC OIP event is next week and again it is packed with a wide range of technical presentations from TSMC, top semiconductor, EDA, and IP companies, plus long time TSMC partner and ASIC provider Open-Silicon, a SiFive Company. You can see the full agenda HERE. ​

AI is revolutionizing and transforming virtually every industry in the digital world. Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher memory bandwidth. ASIC platforms enable AI applications through training in deep learning and high speed inter-node connectivity, by deploying high speed SerDes, a deep neural network DSP engine, and a high speed high bandwidth memory interface with High Bandwidth Memory (HBM) within a 2.5D system-in-package (SiP). Open-Silicon’s implementation of a silicon-proven ASIC platform with TSMC’s FinFET and CoWoS® technologies is centrally located within this ecosystem.

Open-Silicon’s first HBM2 IP subsystem in 16FF+ is silicon-proven at 2Gbps data rate, achieving bandwidths up to 256GBps, and being deployed in many ASICs. The data-hungry, multicore processing units needed for machine learning require even greater memory bandwidth to feed the processing cores with data. Keeping pace with the ecosystem, Open-Silicon’s next generation HBM2 IP subsystem is ahead of the curve with 2.4Gbps in 16FFC, achieving bandwidths up to >300GBps.

This 7nm ASIC platform is based on a PPA-optimized HBM2 IP subsystem supporting 3.2Gbps and beyond data rates, achieving bandwidths up to >400GBps. It supports JEDEC HBM2.x and includes a combo PHY that will support both JEDEC standard HBM2 and non-JEDEC standard low latency HBM. High speed SerDes IP subsystems (112G and 56G SerDes) enable extremely high port density for switching and routing applications, and high bandwidth inter-node connections in deep learning and networking applications. The DSP subsystem is responsible for detecting and classifying camera images in real time. Video frames or images are captured in real time and stored in HBM, then processed and classified by the DSP subsystem using the pre-trained DNN network.

Implementation challenges for AI ASICs include design methodologies for advanced FinFET nodes, physical design of large ASIC >300 mm2 running at GHz speed, power and timing closure, system level power and thermal and timing signoff. Open-Silicon has overcome these challenges with advanced implementation strategies that enable Advanced On-Chip Variations (AOCV) flow for physical design and timing closure, correlation between implementation and signoff that results in faster design convergence, an advance node power plan and validation techniques, and system level signal and power integrity signoff for a complete 2.5D SiP. Additionally, various in-house development tools help debug and analyse the design data through physical design phases, thus speeding convergence of complex designs.

Open-Silicon’s DFT methodology enables the test and debug challenges in large ASIC designs by incorporating methods such as core wrappers, hierarchical BIST/scan, compression, memory repair, power aware ATPG and enablement of wafer probing to ensure quality KGD before 2.5D assembly, interconnect test between ASIC and HBM, and incorporating design practices recommended by TSMC CoWoS® to improve 2.5D SiP manufacturing and yield.

Open-Silicon’s ASIC design and test methodology, low area high performance HBM2 IP subsystem, and its experience in high speed SerDes integration and DSP subsystem implementation, offer best-in-class custom silicon solutions for next generation AI and high performance networking applications.

Who: Bhupesh Dasila, Engineering Manager – Silicon Engineering group, Open-Silicon
What: Custom SoC Platform with IP Subsystems Optimized for FinFET Technologies Enabling AI Applications
When: Wednesday, October 3 2018, 1:00 pm
Where: EDA/IP/Services Track, Santa Clara Convention Center

Open-Silicon is exhibiting at Booth, #907

The TSMC Open Innovation Platform®(OIP) Ecosystem Forum is a one-of-a-kind event that brings together the semiconductor design chain community and approximately 1,000 director-level and above TSMC customer executives. The OIP Forum features a day-long, three-track technical conference along with an Ecosystem Pavilion that hosts up to 80 member companies.

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Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm
Categories: EDA, Fractal Technologies, IP, TSMC

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where timing and power closure will work regardless. Such an issue would only be uncovered during final SPICE netlist checks. Another potential problem could include a case where LEF does not match GDS, completely slipping through the cracks, through full synthesis, and would only be caught during chip level DRC or LVS. This would ultimately require updates to the IP as well as re-synthesis (more slippage).

How can one avoid these potential problems? Simple, with Fractal’s Crossfire QA suite. Fractal is your specialized partner for IP qualification. Crossfire can help you deal with design view complexities, increasing amount of checks required to correctly QA an IP, and the difficulties of dealing with excessive volumes of data.

Crossfire supports over 30 standard design formats, from front-end to back-end, including simulation and schematic views, binary databases such as Milkyway, OpenAccess, and NDM, documentation, and custom formats such as Logic Vision and Ansys APL. Any other ASCII based custom formats can also be easily integrated into the tool.

Getting back to the scope of this article, the recommended baseline of checks can be separated into three sections: cell and pin presence for all formats, back-end checks, and front-end related checks.

Cell and Pin Presence Checks
Although consistency checks such as cell and pin presence may sound trivial, and for the most part, they are, one cannot sweep such an important task under the rug. Don’t be surprised if an IP or standard cell library from a well-known IP vendor is delivered with inconsistencies between the various formats, including cell and pins names, port direction, and hierarchy differences.

Back-end Checks
Ensuring layout related consistencies across all back-end related formats is an important part of the IP QA qualification. Pin labels and shape layers must match across all layout and abstract formats. All layout formats such as GDS, Oasis, Milkyway CEL, NDM and OpenAccess layout views must directly match across the board. When comparing a layout to an abstract format such as LEF, Milkyway FRAM or NDM frame, one must ensure that all layer blockages correctly cover un-routable areas in the layout. On top of that, pin shapes and layers must match in order to guarantee a clean DRC/LVS verification down the line.

Other important checks to consider include area attribute definitions for non-layout formats which must match the area defined by the boundary layers for various layout formats. IP and standard cell pins must be accessible by the router and for non-standard cell related IP, pin obstruction needs to be checked in order to ensure accessibility. In some cases, ensuring that all pins are on a pre-defined grid can also be a necessary task. In the end, these checks will ensure a quicker and less error-prone P&R execution.

Front-end Checks
Front-end checks can be broken into seven separate sections: timing arc, NLDM, CCS, ESCM/EM, NLPM, functional characterization, and functional verification. In this blog, we’ll be covering the latter two related to functional checks. The first five sections related to characterization deserve an article all on their own, therefore, they will be covered in an upcoming blog.

Functional characterization checks ensure the timing arcs are defined correctly when compared the given Boolean functions for formats like Liberty, Verilog, and VHDL. Other checks include power down function correctness, ensuring related power and ground pins are defined correctly when compared to spice netlists or UPF models (correct pins are extracted from spice by traversing the circuits defined in the spice format). We also recommend checking related bias pins and whether input pins are correctly connected to gate or antenna diodes.

When dealing with standard cell libraries, it is important to establish the Boolean equivalence of all formats that describe the behavior of a cell. This will ensure that all formats behave in the same manner when dealing with functionality during various front-end related timing simulations.

What else can Crossfire do?
Crossfire is technology independent. From a tool perspective, the differences include:

  • Exponential data size growth (up to 2x when compared to previous node)
  • Introduction of new design formats (i.e. NDM)
  • Number of corners increasing drastically in newer nodes (i.e. FinFet based)

As a tool, Crossfire only has to differentiate between standard cell libraries and all other IP (memories, digital, analog, mixed-signal, etc.). Some checks, such as abutment or functional verification, are designed specifically for standard cell libraries.

Crossfire is a proven validation tool used by various Tier 1 customers. All checks and formats supported by Crossfire are based upon direct cooperation with our customers. Customers moving from “old” to “new” technology nodes automatically get all the checks and format support developed for and used by Tier 1 customers. This cycle of shared knowledge is passed on from one technology node to another.

Conclusion
IP qualification is an essential part of any IC design flow. A correct-by-construction approach is needed since fixing a few bugs close to tapeout is a recipe for disaster. Given that, IP designers need a dedicated partner for QA solutions that ensures the QA needs of the latest process nodes are always up-to-date. In-house QA expertise increases productivity when integrated with Crossfire. All framework, parsing, reporting, and performance optimization is handled by the tool. On top of that, with a given list of recommended baseline checks, we ensure that all customers use the same minimum standard of IP validation for all designs.

TSMC OIP
The Crossfire team and I will be at a booth in the TSMC OIP exhibit hall next week giving out free copies of our Fabless book, discussing the need for IP qualification, and demonstrating the latest Crossfire software. I hope to see you there!

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UMC and GF or Samsung and GF?

UMC and GF or Samsung and GF?
by Daniel Nenni on 09-17-2018 at 7:00 am
Categories: Foundries, GlobalFoundries, Samsung Foundry, TSMC
3 Comments

One of the interesting rumors in Taiwan last week was the possibility that UMC and GF will do a deal to merge or UMC will buy some GF fabs. I have talked to quite a few industry experts about it and will talk to more this week at the GSA US Executive Forum (more at the end). The US Executive Forum is what they call a C Level event which means it is invitation only and expensive.

This year’s program looks very good. Notice the heavy AI emphasis, as I have said many times before AI will touch most every chip and will keep pushing the leading edge processes, absolutely. EDA CEOs Wally Rhines and Aart de Geus will be there. Wally does a great “Industry Vision” loaded with facts and figures and Aart is not afraid to ask the difficult questions on his panel so both of these talks should be interesting.

Keynote: Looking To The Future While Learning From The Past, Daniel Niles / Founding Partner / AlphaOne Capital Partners

Keynote: Convergence of AI Driven Disruption: How multiple digital disruptions are changing the face of business decisions, Anthony Scriffignano / Senior Vice President & Chief Data Scientist / Dun & Bradstreet

Significance of AI in the Digitally Transformed Future
This session will discuss how developments in machine learning, deep learning and AI are impacting technology segments and market verticals and the significance of Artificial Intelligence in the Digitally Transformed Future.

AI and the Domain Specific Architecture Revolution
Wally Rhines / President and CEO / Mentor, a Siemens Business

AI Driven Security
Steven L. Grobman / Senior Vice President and CTO / McAfee

Innovating for AI in Semis and Systems

AI Accelerators in the Datacenter Ecosystem
Kushagra Vaid / General Manager & Distinguished Engineer – Azure Infrastructure / Microsoft

Delivering on the promise of AI for all – from the data center to the edge of cloud
Derek Meyer / CEO / Wave Computing

Driving the Evolution of AI at the Network Edge
Remi El-Ouazzane/Vice President and COO, Artificial Intelligence Products Group / Intel

The Physics of AI: Architecting AI systems into the Future
Sumit Gupta / Vice President AI, ML and HPC / IBM

AI Panel Discussion
The panel will discuss the innovations in the semiconductor and systems space that are empowering Artificial Intelligence and the collaboration opportunities between semiconductor and systems players to enable emerging markets.

Moderator:
Aart de Geus / Chairman and Co-CEO / Synopsys

Panelists:
– Derek Meyer
– Sumit Gupta
– Kushagra Vaid
– Remi El-Ouazzane

Keynote: Long Term Implications of AI & ML
Byron Reese / CEO, Gigaom / Technology Futurist / Author

VIP Reception
Book signing by Byron Reese
The Fourth Age: Smart Robots, Conscious Computers, and the Future of Humanity

Back to the UMC GF Samsung rumor. Remember, GF has built-out fabs in Singapore, the US, and Europe. GF also has the IBM patents and technology plus the ASIC group which has been spun out. Think about UMC’s pros and cons and see if they match up to GF’s assets and keep in mind, whatever UMC does not need Samsung may want. The ASIC business for example (UMC has Faraday). It would also give GF’s owner a somewhat graceful exit from the semiconductor industry. If you combine UMC and GF it gets you a $5B pure-play foundry which is much closer to TSMC’s $15B.

Of course Samsung could just buy GF outright so there is always that. Just a rumor of course but not unlike the “GF buys IBM semiconductor” rumor we started a while back: GLOBALFOUNDRIES Acquires IBM Semiconductor Unit!

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2018 Semiconductor Winners and Losers

2018 Semiconductor Winners and Losers
by Daniel Nenni on 09-12-2018 at 7:00 am
Categories: Foundries, TSMC
1 Comment

This is an ongoing conversation inside the semiconductor ecosystem, especially when I am traveling. Everyone wants to know what is going on here or there and since I just returned from Taiwan I will post my thoughts. Last week was also my birthday which was cut short due to the time change but I did get preferential treatment on the flight and at the hotel. Upgrades, champagne, treats, and a full-fledged cake from Hotel Royal in Hsinchu. Either I haven’t traveled on my birthday before or they didn’t roll out the red carpet last time or I would have remembered this, absolutely.

My choice for #1 winner is of course TSMC. They are having a great year and will continue to do so, my opinion. GF ending 7nm put AMD firmly in place at TSMC, Intel is rumored to be moving more products to TSMC, and of course Apple and the rest of the industry has already taped-out to TSMC 7nm so get the marching bands and the dragon dance ready for the end of year celebration.

One note about the Intel move, it is being reported that processors (Coffee Lake) are being moved to TSMC. I find this highly unlikely. Intel 14nm is in no way compatible to any TSMC process so this would be a redesign and why would Intel do that? It is much more likely that mobile chips would be retargeted for TSMC (SoCs, modems, IoT, etc…). Remember, the Intel Silicon Engineering Group is now run by Jim Keller. Jim was at Apple, AMD, and Tesla before Intel so he knows TSMC. Maybe even the next generation FPGAs since Intel is going to be short on 10nm and the ex Altera folks are very TSMC experienced. Or maybe the GPUs since TSMC is very good at GPUs (NVIDIA). There is a forum thread on this you may want to take a look at: Intel 14nm capacity issue.

Broadcom is another winner. Hock Tan keeps changing the rules of the semiconductor game and there is no telling what he will do next but you can bet it will be disruptive. We all scratched our heads when Broadcom acquired Computer Associates for $18.9B in cash. Hock clarified his strategy in the quarterly call:

Speaking of acquisitions, before I turn this call back to Tom to talk about the financials in greater detail, let me perhaps take a few more minutes and talk about CA Technologies. The number one question we get from when we get with CA is, why did we choose to buy? Cut to the chase. We’re buying CA because of the customers and their importance to these customers. CA sales mission critical software to virtually all of the world’s largest enterprises. These are global leaders in key verticals including financial services, telecoms, insurance, healthcare and retail. And CA does it a scale fairly unique to the infrastructure software space. This can only come from longstanding relationships with these customers that spend several decades. In other words, these guys are deeply embedded… https://www.legacy.semiwiki.com/forum/f302/interesting-notes-broadcom-q3-2018-call-10764.html

I also consider GF a winner with their new boutique foundry pivot. I covered this in a previous post GLOBALFOUNDRIES Pivoting away from Bleeding Edge Technologies.

For losers I would start with Intel. 10nm is still in question and even more loserish is the way they disposed of their CEO who spent his entire career at Intel. I cannot believe a Silicon Valley icon like Intel would do such a despicable thing to a 36 year veteran. Clearly it was sleight of hand, waving one hand so you do not see what the other is doing, or not doing in this case. Replacing a questionable CEO with a temp CEO who has publicly declared he does not want to be CEO while you spend months looking for a new CEO? The big question I have is: Why is the Intel Board of Directors NOT being held accountable for this blunder?Correct me if I’m wrong here but this does not pass the corporate smell test.

Let’s continue this discussion in the comments section. Who do you think the semiconductor winners and loser of 2018 will be?