In 2014 Apple released the iPhone 6 which included the first SoC built on a TSMC (20nm) process. This phone started what many call a “Super Cycle” of people upgrading. According to Apple, they now have more than 1 billion activated devices so this super cycle could be seriously super, absolutely.
Continue reading “Apple iPhone Super Cycle Update!”
High Bandwidth Memory ASIC SiPs for Advanced Products!
When someone says, “2.5D packaging” my first thought is TSMC and my second thought is Herb Reiter. Herb has more than 40 years of semiconductor experience and he has been a tireless promoter of 2.5D packaging for many years. Herb writes for and works with industry organizations on 2.5D work groups and events at conferences around the world. I have worked with Herb on various conferences and recommend him professionally at every opportunity.
Next month Herb is moderating a webinar with Open-Silicon on High Bandwidth Memory ASIC SiPs for High Performance Computing and Networking Applications on Tuesday, September 19, 2017 from 8:00 AM – 9:00 AM PDT. I strongly suggest you register today because this one will fill up!
This Open-Silicon webinar, moderated by Herb Reiter of eda 2 asic Consulting, Inc., will provide an overviewHBM2 ASIC SiPs (System in a Packages) for density and bandwidth-hungry systems based on silicon proven Open-Silicon’s High Bandwidth Memory (HBM2) IP subsystem solution. . Attendees will also learn about the system integration aspects of 2.5D HBM ASIC SiP, and performance results of various memory access patterns suiting different applications in High Performance Computing and Networking.
The webinar also summarizes silicon validation results of a 2.5D HBM2 ASIC SiP validation/evaluation platform, which is based on Open-Silicon’s HBM2 IP subsystem in TSMC’s 16nm in combination with TSMC’s CoWoSTM 2.5D silicon- interposer technology and HBM2 memory They will discuss the significance of the results and how they demonstrate functional validation and interoperability between Open-Silicon’s HBM2 IP subsystem and the HBM2 memory die stack. Attendees will learn about HBM2 memory and its advantages, applications and use cases.
The panelists will also discuss the HBM2 IP subsystem roadmap and Open-Silicon’s next generation multi-port AXI (Advanced eXtensible Interface) based HBM2 IP subsystem development targeting 2.4Gbps per-pin data rates, and beyond, in TSMC’s 7nm technology. This webinar is ideal for chip designers and system architects of emerging applications, such as high performance computing, networking, deep learning, neural networks, virtual reality, gaming, cloud computing and data centers…
For those of you who don’t know, TSMC’s CoWoS® (Chip-On-Wafer-On-Substrate) advanced packaging technology integrates logic computing and memory chips in a 3-D way for advanced products. CoWos targets high-speed applications such as: Graphics, networking, artificial intelligence, cloud computing, data center, and high-performance computing. CoWos was first implemented at 28nm in 2012 and continues today at 20nm and 16nm. Next up is 7nm which should be a banner node for CoWos, absolutely.
About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software, IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities.
The company has partnered with over 150 companies, ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. To learn more, visit www.open-silicon.com
TSMC OIP Ecosystem Forum 2017 Preview!
The TSMC OIP Ecosystem Forum is upon us again. I have yet to meet a disappointed attendee so it is definitely worth your time: Networking with more than 1,000 semiconductor professionals, the food, mingling with the 50+ EDA, IP, and Services Companies, the food, and of course the content. The 7nm and 7nm EUV updates alone are worth the trip, absolutely! And remember, it is September 13th at the very convenient Santa Clara Convention Center.
Applying ISO 26262 in a Fabless Ecosystem – DAC Panel Discussion
The fabless movement was instrumental in disaggregating the semiconductor industry. Vertical product development at the chip and system level has given way to a horizontal structure over the years. This organization of product development has been doing an admirable job of delivering extremely reliable products. However reliable for a phone is not reliable enough for an autonomous vehicle with a service life of up to and over a decade. This issue was recognized years ago and lead to the development of the ISO 26262 standard in 2011.
ISO 26262 deals with the electronic systems in a car, with the goal of avoiding systematic errors and faults, as well as helping to deal with random errors. It applies to non-critical systems such as infotainment and also to critical systems like brakes, steering and autonomous operation.
Electronic systems in cars are often produced by fables semiconductor companies and frequently incorporate 3[SUP]rd[/SUP] party IP. Applying ISO 26262 to products developed in a dispersed manner is leading to changes that are affecting every member of the supply chain. To explore these impacts Mentor hosted a panel discussion at DAC in Austin. The panel had representation from members of each element in the supply chain affected by ISO 26262.
At first glance it makes sense that Mentor would be on the panel as an embedded OS supplier, but in the context of ISO 26262, the design tool providers are also an essential link in the chain. Rob Bates, Chief Safety Officer for the Embedded Division, spoke on behalf of Mentor. Also on the panel was Volker Politz, VP Segment Marketing at Imagination Technologies, who talked about the changes necessitated for IP developers. Jim Eifert Automotive Architect at NXP provided insight from the automotive system integration perspective. Lastly, Lluis Paris, Director, Worldwide IP Alliance at TSMC shed light on how the foundries for fabless semiconductor companies have shifted the way they work in the automotive sector.
There was a round of introductory comments by each panelist. Jim from NXP said that a big benefit of the standard is that there is common terminology that buyers can use when speaking with suppliers. Lluis from TSMC talked about how the role of a fabless foundry has shifted from just supplying silicon to developing an automotive platform to enable and encourage ISO 26262. This stems from the need for more extensive sustaining engineering and additional product documentation among other things. TSMC has added the role of safety manager to their organization as part of this endeavor.
Volker from Imagination pointed out that now the IP provider is in the middle. In some ways they are partnered with their customer’s engineering department. Products fuse together external and internal IP and design work. The biggest change for him is that there is now a more formal way for them to work together. Rob from Mentor added that prior to ISO 26262 companies were just continuing to engage in their previous practices. The standard has really changed the way the companies involved operate. He cited the example of TSMC, who is rebuilding many aspect of how they deal with automotive designs from the ground up.
The first question put to the panel was, does IP have to be certified?
TSMC was quick to point out that IP does not have to be certified, but that the process for making the chip does. This arises because in many cases the applications for the IP are so large that the IP vendor can’t possibly know the use-case that is applicable. Imagination added that there is not really a certification for IP, but the vendors can help by delivering the necessary documentation with their IP. IP vendors can help contribute. NXP said that the car is what is certified, and the key is to turn over at each step of the development the correct documentation to facilitate this and create traceability.
The next question asked if embedded software should be considered IP.
Mentor responded by saying that the embedded software resides on the chip which is closer to the customer. Development tools are closely linked to the embedded code, so they too are tied to the standard in some way. NXP agreed that the embedded code needs to comply with the standard and wished there was more explicit requirements for development tools.
The next question asked if the car is ‘certified’ then what documentation is needed to create traceability up the chain from the components?
TSMC stated that the foundry has to do a larger number of things under ISO26262. These include special SPICE and reliability models, along with aging models. The car needs to be traceable after 18 years in case there is an issue down the road. The foundry needs to keep the process viable for a long time and may even potentially need to go back to the wafer info after many years. NXP added that the standard requires a quantitative approach to quality. As part of this it can go to the level of looking at parts per billion failure rates.
Mentor sees that ISO 26262 puts a burden on the tool users to qualify the tools they are using for design. However, realistically this is not something the tool users can take on by themselves. The tool vendor must play a role. This is why they created the Mentor Safe Program.
The panelists were asked, despite the increased level of work required, whether or not they saw benefits in following the process in terms of improved reliability and safety.
TSMC said that they were already doing many of the things that are needed. They feel that instead of a quality increase, what they are seeing is better lifecycle planning. Imagination answered by saying that they are seeing some improvements, but they are also seeing improved reusability. NXP followed by saying that their safety process was already working, but they now have a better documentation process. Mentor feels that the standard helps people look at what they were doing, and that it can only help.
Then came the question of how the standard should evolve. TSMC feels that the hardware side of the specification is comprehensive and stable. However, there is more work that will need to be done on the software side. Imagination would like to see more focus on real integrity. They feel it is important that people are committed to the process and this is the only way the data is reliable. They also expect additions in the area of security, which is at its core a safety issue. NXP amplified that concern by saying that security is absolutely a safety issue, and they are very concerned about hacking. Mentor also concurred that security is something that needs to be addressed more fully in the future versions of ISO 26262.
The panel closed with a question on what new things would be beneficial to the ecosystem. TSMC feels that there is a good ecosystem in place for silicon. They see further ecosystem work occurring in the customer infrastructure. Imagination reiterated the point that they felt that security should be a priority. Imagination said that the EDA companies can also do a lot to help. The more EDA players do – for instance fault injection – the easier it will be to meet the spec. NXP really wants to see chip level design flows made easier to qualify. If they can get a packaged solution it will reduce their need for spreadsheets.
Mentor agreed with this perspective and feels that EDA vendors can help make it possible to adhere to the standard more easily. For instance defect tracing analysis could be added, rather than it being an after-the-fact activity. Mentor sees value in adding capabilities to make it easier to qualify. At the end of the day Mentor feels these same practices and features have wider applicability. They want to move the process out of the automotive space. It could improve customer satisfaction in a wide range of products. Mentor did a great job of pulling together the panel participants and facilitating the discussion. With their Mentor Safe program, it is clear they are serious about automotive safety. For more information on Mentor’s work in this area, please look at their website.
Standard Node Trend
I have previously published analysis’ converting leading edge logic processes to “standard nodes” and comparing standard nodes by company and time. Recently updated details on the 7nm process node have become available and in this article, I will revisit the standard node calculations and trends.
Designing at 7nm with ARM, MediaTek, Renesas, Cadence and TSMC
The bleeding edge of SoC design was on full display last month at DAC in Austin as I listened to a panel session where members talked about their specific experiences so far designing with the 7nm process node. Jim Hogan was the moderator and the panel quickly got into what their respective companies are doing with 7nm technology already. Earlier this year we heard about the first 10nm chip being used for the Qualcomm Snapdragon 835 chip, so I was quite interested to here what the next smaller node at 7nm was going to bring us.
Continue reading “Designing at 7nm with ARM, MediaTek, Renesas, Cadence and TSMC”
TSMC Unveils More Details of Automotive Design Enablement Platform
At this year’s Design Automation Conference (DAC), TSMC unveiled more details about the design enablement platforms that were introduced at their 23[SUP]rd[/SUP] annual TSMC Technology Symposium earlier this year. I attended a presentation on TSMC’s Automotive Enablement Platform held at the Cadence Theater where TSMC’s Tom Quan gave a great overview of their status. Before diving into automotive, as a quick review, Tom updated us on all four of the segments covered by their enablement platforms, those being Mobile, High Performance Computing, Automotive and Internet of Things. Compound annual growth rate of wafer revenue from each of these areas was 7%, 10%, 12% and 25% respectively. Mobile consumes wafers from 28HPC+, 16FFC, 10nm and is now seeing some 7nm starts. HPC is in production at 16FF+ with newer designs targeting 7nm. IoT has the broadest breadth of wafer usage including 90nm, 55ULP, 40ULP, and 28HPC+ with 7nm ready for design starts.
Automotive, the subject of Tom’s presentation, is ready for design starts using 16FFC process. Tom started his presentation by giving a quick overview of the different types of ICs now being used in the automotive space. The biggest driver of platform complexity comes from infotainment and the growing space of ADAS (Advanced Driver Assistance Services). ADAS alone has several categories of applications and associated ICs including using vision, radar and audio capabilities for detection, avoidance, varying degrees of autonomous driving features, voice recognition, natural language interfaces, vision enhancement, and the list goes on. Overlaid on the traditional areas of power-train, engine control, chassis and suspension, communications and infotainment are now safety and security. All these functions are represented by more than 40 customers who have done over 600 tape-outs to TSMC with more than 1 million 12 inch equivalent wafers worth of ICs being shipped.
TSMC has put a tremendous amount of work into capturing this market building upon their successful Open Innovation Platform, better known to many of us as TSMC OIP. The whole idea of OIP is to bring together the thinking of customers and partners to enable an ecosystem that speeds time-to-market and ultimately shortening time-to-money for all involved. TSMC OIP boasts over 16 years of collaboration with more than 100 ecosystem partners and spans 13 technology generations that includes over 14,000 IPs, 8200+ tech files and 270 PDKs for 90+ EDA tools. The enablement platforms build on this foundational work ensuring that all of the right building blocks and tools are in place to enable designs in a given end market – in this case automotive.
As an example, and since TSMC was presenting at the Cadence Theater, we can look at the collaboration between TSMC and Cadence. Their collaboration in automotive started in 2015 with a focus on identifying needs and solutions to ensure conformance with the two main standards in this space which are AEC-Q100 and ISO-26262. Functional safety was a key area of collaboration and Cadence and TSMC started by training their engineers on functional safety requirements for the automotive space. Within the last two years, Cadence alone has trained over 100 engineers, many of which have been officially certified by an outside agency. Together, TSMC and Cadence have engaged with customers doing automotive ICs and IPs and as a result, Cadence developed a portfolio of interface IPs in TSMC’s 16FFC process supporting those customers. Many of these IP already meet AEC-Q100 requirements for Grade 2 temp range and Cadence has committed to qualify their controller IPs to be ISO 26262 ASIL-ready.
With respect to design tools and flows, in the second half of 2016, TSMC and Cadence worked to define a methodology for fault injection simulation and functional safety campaign management. In that time frame Cadence gained ISO 26262 tool compliance on 30+ tools in analog-mixed-signal, digital verification and front-end digital implementation and signoff flows. This work has also now prompted the collaboration to work on ‘reliability-centric’ design flows for 16nm and below including features such as aging simulations, self-heating, electro-migration analysis, FIT (failures in time) rate calculations and yield simulations.
TSMC wraps this effort up under another TSMC umbrella called TSMC9000. TSMC9000 and associated programs for TSMC Library and IP are quality management programs that aim to provide customers with a consistent, simple way to review a set of minimum quality requirements for libraries and IP designed for TSMC process technologies. The TSMC9000 team monitors ongoing IP quality and their requirements are documented and constantly revised to keep IP quality requirements up-to-date. TSMC IP Alliance members submit required data to TSMC for assessments. Assessment results are posted online so that customers can see the results and scores and understand the IP confidence level and/or risk of using a given IP. Having these assessment results readily available can significantly shorten design lead time and lower total cost of ownership for automotive IC and systems providers.
TSMC9000A (A for automotive) is based on requirements from ISO 26262 and AEC-Q100 to cover IP quality, reliability and safety assessment. It includes automotive grade IP at the 16FFC node targeted to automotive ADAS and Infotainment applications. Most of the current automotive IP has completed technology qualification for AEC-Q100 grade 1 up to 150[SUP]0[/SUP] C (Tj) and have been re-qualified with automotive-specific DRC/DRM decks. These IP are also ISO 26262 ASIL ready including safety manuals, FMEA/FMEDA, and ASIL B(D) certification.
In summary, TSMC’s automotive design enablement platform on 16FFC is ready to go. It will be interesting to see by the next DAC how far this platform has progressed both in terms of content and usage as the world progresses towards autonomous self-driving vehicles.
See also:
TSMC Design Platforms Driving Next-Gen Applications
TSMC @ #54DAC!
TSMC has been an ardent supporter of DAC for the last 18 years which has brought in the other foundries because, as the industry leader, wherever TSMC goes the other foundries naturally follow. The exception of course is Intel Custom Foundry because they march to the beat of a different drummer, if you know what I mean. The CoFluent group of Intel does exhibit at DAC, yes Intel became an EDA company with the purchase of French ESL company CoFluent in 2011. I’m not sure who their customers are but probably not the growing number of companies that compete with Intel due to their acquisitions but I digress…
This year TSMC has some notable speakers that you may want to catch:
TECHNICAL PANEL
Minimizing IC Power Consumption: Top Down or Bottom up Design Methodology. What is the Starting Point?
Moderator – John Blyler – Electronic Design Mag.
Aditya Mukherjee – Microsoft
Tim Saxe – QuickLogic Corp.
Abhishek Ranjan – Mentor, A Siemens Business
Ronald Martino – NXP Semiconductors
Lluis Paris – TSMC
Jon Adams – ON Semiconductor
Lluis Paris is Director of World Wide IP Alliance at TSMC and a recognized IP expert, in fact he is the top IP person I know and that is saying a lot because I know many. Lluis came to TSMC from the Emerging Memory Technology acquisition where he was COO. Not only does Lluis have a PhD in Microelectronics, he also has an MBA so he is definitely worth your time. I also know Tim Saxe from my Zycad and GateField FPGA days. Tim has a PhD in Electrical Engineering from Stanford and is a straight shooter with YEARS and YEARS of experience so he is definitely worth listening to.
The panel is on Monday at 3:30pm in the Convention Center, Ballroom G and I will be at this one. Lluis is also participating in the Mentor Booth Panel on the Impact of ISO 26262 on the fabless ecosystem on Tuesday at 5pm.
Tom Quan is also one of my favorite TSMC presenters. Tom has been at TSMC for ten years and before that he was an EDA staple. Prior to EDA, he was a Design Engineer at Intel. Tom is an AMS expert so that is where you can usually find him. This year he is quite busy:
LUNCH PANELS
Cadence: High Performance Digital Design at 7nm
Tuesday 12:00pm at the Convention Center – Ballroom B & C
Synopsys: Custom Compiler in 7nm
Tuesday 11:30am Hilton Hotel, 6th Floor, Austin Grand Ballroom H
BOOTH PRESENTATIONS
Synopsys: Design Enablement for HPC, Mobile, IoT and Automotive Applications
Monday 2:00pm
Cadence: TSMC Automotive Design Enablement Platform
Tom Quan Tuesday 2:00pm, Chek-San Leong Tuesday at 4:00, and Captain Liu Wednesday 1:30pm.
Captain Liu spent his career in EDA (Springsoft/Synopsys) before coming to TSMC two years ago. Captain is also busy at DAC:
BOOTH PRESENTATIONS
Cadence: TSMC-Cadence Collaboration for Digital Design Enablement at 7nm Monday at 11:30am and 1pm.
Synopsys: Design Enablement for HPC, Mobile, IoT and Automotive Applications Tuesday at 1:30pm.
ANSYS: Tool Flow Verification Monday at 2:45pm.
My good friend Willy Chen will be on the Synopsys breakfast panel: ARM, Synopsys and TSMC collaboration to enable high performance design with the latest processors and FinFET processes, including 7nm Monday morning. I will be at that one as well.
Last but not least Libby Aston and Chek-San Leong will be presenting Design Enablement for HPC, Mobile, IoT and Automotive Applicationsat the Chip Estimate booth on Tuesday and Wednesday at 1:30pm respectively.
You can see all of the DAC events HERE.
Please notice that TSMC 7nm is all over DAC this year meaning that we will see production chips in 2018, absolutely! Exciting times, I hope to see you there!
Live from the TSMC Earnings Call!
Last week I was invited to attend the TSMC earnings call at the Shangri-la Hotel in Taipei which was QUITE the experience. I generally listen in on the calls and/or read the transcripts but this was the first one I attended live. I didn’t really know what to expect but I certainly did NOT expect something out of Hollywood. Seriously, there were photographers everywhere taking hundreds of pictures. I was sitting front row center and as soon as the TSMC executives sat down there was a rush of paparazzi and the clicking sounds were deafening. It was a clear reminder of how important TSMC is in Taiwan, and the rest of the world for that matter.
The most interesting news for the day was that 10nm is progressing as planned with HVM in the second half of this year. In fact, 10nm should account for 10% of TSMC wafer revenue this year (Apple). There had been rumors that foundry 10nm was in trouble (fake news) but clearly that is not the case for TSMC. In fact, according to C. C. Wei:
Although N10 technology is very challenging, the yield learning progression has been the fastest as compared to the previous node such as the 20- and 16-nanometer. Our current N10 yield progress is slightly ahead of schedule. The ramp of N10 will be very fast in the second half of this year.
C.C. also gave an encouraging 7nm update:
TSMC N7 will enter risk production in second quarter this year. So far, we have more than 30 customers actively engaged in N7. And we expect about 15 tape-outs in this year with volume production in 2018. In just 1 year after our launch of N7, we plan to introduce N7+ in 2018. N7+ will leverage EUV technology for a few critical layers to save more immersion layers. In addition to process simplification, our N7+ provides better transistor performance by about 10% and reduces the chip size by up to 10% when compared with the N7. High volume production of N7+ is expected in second half 2018 — I’m sorry, in second half of 2019. Right now, our focus on EUV include power source stability, pellicle for EUV mask and stability of the photoresist. We continue to work with ASML to improve the tool productivity so that it can be ready for mass production on schedule.
And last but not least 5nm:
We have been working with major customers to define 5-nanometer specs and to develop technology to support customers’ risk production schedule in second quarter 2019, with volume ramp in 2020. Functional SRAM in our test vehicle has already been established. We plan to use more layers of EUV in N5 as compared to N7+.
The other interesting technology update was InFO:
First, we expect InFO revenue in 2017 will be about USD 500 million. Now we are engaging with multiple customers to develop next-generation InFO technology for smartphone application for their 2018, 2019 models. We are also developing various InFO technologies to extend the application into high-performance computing area, such as InFO on substrate, and we call it InFOoS; and InFO with memory on substrate, InFO-MS. These technologies will be ready by third quarter this year or first quarter next year.
If I remember correctly, InFO contributed $100M last year (Apple) so this is great progress. By the way, now that I have seen the facial expressions that go with the voices during the Q&A I can tell you that C.C. has a very quick wit. I had pity for the analysts who tried to trip up C.C. and get inappropriate responses from him.
Mark Lui talked about ubiquitous computing and AI which reminded me why TSMC is in the dominant position they are today. As a pure-play foundry TSMC makes chips for all applications and devices. Ubiquitous says that computing can appear anytime and anywhere meaning all of those mobile devices TSMC has enabled over the past 30 years will continue to evolve making the TSMC ecosystem worth its weight in silicon.
I also have a new perspective on the analysts that participate in the Q&A after sitting amongst them. I have no idea how much they get paid for what they do but I’m pretty sure it is too much.
Here is my favorite answer for Q1 2017:
Michael Chou Deutsche Bank AG, Research Division – Semiconductor Analyst Okay, the next question, sir, management mentioned the log scale comparison versus Intel, I think, the 2014, right? So since Intel came out to say that their technology seems to be 3 year ahead of the other competitor, including your company, so do you have any comment on your minimum metal pitch and the gate pitch comparison versus Intel? Or do you have any comment for your 5-nanometer versus Intel 10-nanometer, potential 7-nanometer?
C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – Co-CEO and President Well, that’s a tough question. I think every company, right now, they have their own philosophy developing the next generations of technology. As I reported in the foundry, we work with our customer to define the specs that can fit their product well. So the minimum pitch to define the technology node, we are compatible to the market. But the most important is that we are offering the best solution to our customers’ product roadmap. And that’s what we care for. So I don’t compare that really what is the minimum pitch to define the technology node.
Absolutely!
A PDF of the meeting is HERE. The presentation materials are HERE. I have pages of notes from the event and the trip in general so lets talk more in the comments section and make these analysts green with envy!
TSMC Design Enablement Update
A couple of recent semiwiki articles reviewed highlights of the annual TSMC Technical Symposium recently held in Santa Clara (links here, here, and here). One of the captivating sessions at every symposium is the status of the Design Enablement for emerging technologies, presented at this year’s event by Suk Lee, Senior Director at TSMC. In the broadest sense, design enablement refers to both EDA tools and design IP, developed specifically for the new process node.
TSMC focuses on early engagement with EDA vendors, to ensure the requisite tool features for a new process node are available and qualified, on a schedule that supports “early adopter” customers. As the prior semiwiki articles have mentioned, N10 tapeouts will be ramping quickly in 2017, with N12FFC and N7 soon to follow. So, it was no surprise that the EDA tool status that Suk presented for these nodes was green, usually for multiple EDA vendors (e.g., 3 or 4).
The unique part of Suk’s presentation is the description of key EDA tool requirements presented by the new process node. These offer insights into the additional complexities and design characteristics introduced. Here are some of the new features that struck me as particularly interesting.
stacked vias and via pillars
There are two characteristics of each new process node that are always troublesome for designers, and for the optimization algorithms applied during physical implementation. The scaling of metal and via pitches (for the lowest metal layers) results in increased sheet and via resistance. Correspondingly, this scaling also exacerbates reliability concerns due to electromigration — this issue is magnified due to the increased local current density associated with FinFET logic circuits.
SoC designs at these new nodes need an efficient method to utilize the upper level layers in the overall metallization stack, for reduced RC delay and/or improved electromigration robustness. Suk presented two options that are being recommended for N7 — stacked vias and via pillars. Design rules enabling stacked vias are leveraged by the TSMC Mobile platform, while the expectation is that the High-Performance Computing (HPC) platform designs will need to regularly use via pillars. A via pillar is depicted in the figure below.
Suk highlighted some of the unique EDA tool algorithms needed, to support the prevalent use of via pillars:
- physical synthesis, clocktree synthesis, APR
Physical implementation algorithms need to assess where via pillars are needed — there is a significant interconnect timing improvement versus route track blockage tradeoff assessment required.
- parasitic extraction, static timing analysis, EM, and I*R
The via pillar is a unique geometry. RC extraction tools need to translate this topology into a suitable model for subsequent electrical analysis (EM, I*R), specifically how the current will spread throughout the pillar. EDA vendors have addressed this via design insertion and analysis requirement for N7 — this is fully green.
One area that has me curious that Suk didn’t mention is the yield impact of using via pillars. Commonly, yield enhancement algorithms are exercised near the end of physical implementation, often by attempting to add redundant vias where feasible — perhaps, a via pillar insertion strategy will evolve as a new DFM/DFY option.
“cut metal” masks and coloring
Advanced process nodes have replaced traditional metal interconnect lithographic patterning with spacer-based mandrels and cuts, to realize more aggressive pitch dimensions. The drawn metal layout shapes are translated into drastically different mask implementations, involving the addition of: mandrel shapes (for spacer-based damascene metal etching); “cut masks”; and, metal/cut decomposition color assignment (associated with multi-patterning and successive litho-etch steps). There are optimizations available to reduce the need for multi-patterning of cuts, by adjusting the cut spacing through the addition of metal extensions — the figure below illustrates a simple example.
(From: “ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology”, Han, et al., Proc. SPIE, October, 2015. Note the metal extensions added to align cuts.)
TSMC has worked with EDA vendors to optimize metal and cut mask generation, and multi-patterning decomposition. Flows impacted include physical implementation, LVS, and extraction. Suk’s presentation also briefly mentions that ECO flows with cut metal and metal extensions needed to be updated, as well.
dual pitch BEOL
At the symposium, TSMC introduced an aggressive technology roadmap, including the new N12FFC offering. This technology is intended to offer a migration path for existing 16FF+/16FFC designs.
N12FFC includes an improved metal pitch on lower levels, as compared to N16. Logic blocks would be re-implemented with a 6T cell library, from TSMC’s Foundation IP for N12FFC. Other hard IP would be re-characterized, without new layout. As a result, EDA vendors need to support dual-pitch back-end-of-line (BEOL) IP pin and routing implementations, integrating both new 12FFC and existing 16FFC blocks.
Suk highlighted that the Design Enablement team at TSMC is also introducing technology model support (and qualified EDA tools) to address the reliability challenges of new process nodes, especially the more stringent targets of automotive applications — e.g., advanced electromigration analysis rules, advanced (self-heat) thermal models for local die temperature calculations, device parameter end-of-life drift due to BTI and HCI mechanisms.
The close collaboration between TSMC and the EDA tool developers is fundamental to early customer adoption for emerging technologies. Each new node introduces physical implementation and electrical analysis challenges to conquer. It will be interesting to see what new EDA tool and flow capabilities the N5 process node will require.
-chipguy