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January 20, 2020August 31, 2020

TSMC Q4 2019 “2020 Bellwether” Conference Call Summary

TSMC Q4 2019 “2020 Bellwether” Conference Call Summary
by Daniel Nenni on 01-20-2020 at 6:00 am
Categories: Semiconductor, TSMC
17 Comments

After returning from a week in Southern China I found the TSMC Q4 2019 conference call even more interesting. In China they are preparing for the New Year’s Celebration so everything is very festive but what struck me hardest was the massive investment in infrastructure and security. Semiconductors are of course a big part of that thus the urgent need for China to be semiconductor-self-sufficient, absolutely.

TSMC of course is a valued partner of China and will benefit the most from China’s continued semiconductor boom. If you read between the lines of the TSMC Q4 conference call you will see it more clearly. First let’s look at the technology parts of the prepared statement:

“16-nanometer and below, accounted for 56% of wafer revenue, up from 51% in the third quarter. On a full year basis, 7-nanometer contribution increased from 9% in 2018 to 27% of wafer revenue in 2019. 10-nanometer was 3% and 16-nanometer was 20%. Advanced technologies accounted for 50% of total wafer revenue, up from 41% in 2018.”

It is interesting to note that TSMC 20nm and 16nm shared fabs where 20nm was the sacrificial lamb and 16nm is the cash cow. It was the same with 10nm and 7nm (cash cow). So, what is going to happen now that TSMC is moving 7nm customers to 6nm and 5nm is ramping up this year? Will TSMC break the cycle and have two cash cows in a row? From what I have been told 6nm is an EXCELLENT process and will be VERY competitive on price / performance with both TSMC and Samsung 5nm. In fact, my guess is that TSMC 6nm will even outperform Intel 10nm on density, yield, and most certainly cost.

“Now let’s take a look at revenue contribution by platform…. On a full year basis, smartphone and IoT led the growth with 12% and 33%, respectively, while HPC, automotive and DCE decreased 8%, 7% and 8%, respectively… Overall, smartphone accounted for 49% of our 2019 revenue; HPC, 30%; and IoT, 8%.”

Remember, in 2019 China is second in TSMC revenue (20%) behind the US (60%) but well in front of the other parts of the world and China revenue is on the rise. My guess is that China will be 25% of TSMC’s revenue in 2020 further out pacing Japan, Korea, Taiwan, and the EU, who are all in single digits.

The TSMC smartphone and IoT surge are a very good reflection of the China market.

Samsung is being pushed out of china leaving Apple as the only foreign smartphone supplier in the top 5. Huawei is dominating and Huawei and TSMC go together like peanut butter and jelly. In order to compete the other China smartphone suppliers are forced to follow Huawei into the TSMC ecosystem so it is all about TSMC.

IoT is the interesting one. The number one IoT driver in China is security (cameras) which are EVERYWHERE and backed by AI. 5G is a national priority in China and will increase the abilities of AI on the edge.

For example, in the US we have license plate readers so our local police can identify and recover stolen cars and the criminals that are driving them. The next level is facial recognition where law enforcement can identify known criminals and recover them. China is already at that next level, semiconductors and AI are everywhere and there is no stopping it no matter how you feel about privacy.

“We raised our 2019 CapEx guidance by $4 billion to $14 billion to $15 billion, and we ended up spending $14.9 billion. Our 2020 capital budget is expected to be between $15 billion and $16 billion. Out of the $15 billion to $16 billion CapEx for 2020, about 80% of the capital budget will be allocated for advanced process technologies including 3, 5 and 7-nanometers, about 10% will be spent for advanced packaging and mask-making and about 10% for specialty technologies.”

As I mentioned before, TSMC won the 7nm, 6nm, and 5nm popular vote so do not be surprised if CapEx is again raised and we have another hockey stick of growth in Q4.

“For the full year of 2020, we forecast the overall semiconductor market growth excluding memory to be 8%, while foundry industry growth is forecast to be about 17%. For TSMC, we are confident we can outperform the foundry revenue growth by several percentage points in U.S. dollar term.”

Now that ‘s what I’m talking about… 20% growth. It really is satisfying when hard work pays off.

“Now allow me to talk about our N5 volume production. Our N5 technology is a full node stride from our N7, with 80% logic density gain and about a 20% speed gain compared with 7-nanometer. N5 will adopt EUV extensively and is well on track for volume production in first half this year and with good yield.”

“Finally, I’ll talk about our N3 status. We are working with customers on N3’s design, and the technology development progress is going well. We have many technology options in development and we carefully evaluate all the different approaches. Our decision is based on technology, maturity, performance and cost… We will announce more details about our N3 technology at our TSMC North America Technology Symposium on April 29.“

TSMC N3 will again be FinFET based. We can talk more about this after the Symposium. The Q&A was pretty lame this time but here is the best answer:

“But I can just tell you that whatever you read on the newspaper is not true…”

January 19, 2020July 6, 2020

The Tech Week that was January 13-17 2020

The Tech Week that was January 13-17 2020
by Mark Dyson on 01-19-2020 at 10:00 am
Categories: China, TSMC

In a week where the “phase 1” trade deal between US and China was finally signed, here is all the key news from the semiconductor and technology sector around the world.

After 2 years of an ever increasing trade war, the US and China have signed the so called Phase 1 deal aimed at reducing trade frictions.

Just as important as what is in the phase 1 deal are the items that are left out and are the major items to negotiated for the next phase. This BBC article reviews the major items missing which include the issue of China subsidies to companies in of support it’s “Made in China 2025” policy. Also excluded is the ban on Huawei and further reductions in tariffs that still remain. Let’s hope that progress is made on these more difficult items soon.

According to Gartner, last year Intel regained the number 1 slot for semiconductor companies based on global revenue in 2019 as Samsung dropped to number 2 due to the decline in memory prices and sales in 2019. Overall Global semiconductor revenue dropped 11.9% in 2019 compared to a year ago according to Gartner.

2020 is starting off with a brighter forecast for the year. Semiconductor analyst company Future Horizons is predicting that the global semiconductor market will increase to US$451billion in 2020, this is a 10.2% increase compared to 2019.

This optimism is backed up by initial trade data from Korea, where Korean semiconductor exports rose 12% in the first 10 days of 2020 in a sign that the industry is recovering from the negative effects of the trade war. This is the first time the figures have shown growth since October 2018.

TSMC expects to post revenues of between US$10.2 billion and US$10.3 billion in the first quarter of 2020, representing a 1.4% sequential decrease, but up a massive 44% on a year ago. TSMC also set its capex target this year at between US$15 ~16 billion, up from the US$14.9 billion allocated in 2019 with the majority of capex to be spent on advanced process nodes including 7nm, 5nm and 3nm. TSMC’s Q4 revenue increased to US$10.4bn, up 10.6% sequentially of which 7nm chip shipments accounted for 35% of its total wafer revenues, up from 27% in the prior quarter. Advanced technologies, defined as 16nm and below, accounted for 56% of TSMC’s total wafer sales. In Q4 2019 smartphone revenues accounted for 53% of TSMC’s total wafer revenues, followed by the HPC segment with 29%, IoT with 8%, automotive 4% and digital consumer electronics 3%. In terms of markets, North America remained TSMC’s largest market with a 59% revenue share in Q4 whilst China accounted for 22%. This is up 9% compared to the same period in 2018. With business booming, according to Digitimes, TSMC 7nm process lead time remains at about six months, with tight supply expected to last through 2020

Also according to Digitimes, ASE is rumoured to be supplying to Apple antennas needed for mmWave 5G iPhones and iPad.

Elsewhere AMS has said it is confident it will get shareholder backing for it’s rights issue at it’s EGM on 24th January. The rights issue to raise US$1.84billion will help to partially refinance the US$4.42billion loan AMS took to acquire it’s 59.9% share of Osram.

With the expected recovery of the automotive market and it’s strong demand for SiC products, STMicroelectronics has signed a US$120million multi year supply deal for 150mm Silicon Carbide (SiC) wafers from SiCrystal AG which is part of the ROHM group. The deal adds extra SiC wafer capacity on top of existing deals STM has signed last year with other suppliers like Cree where it signed a multiyear US$250million supply deal and Norstel AB where it has acquired a majority stake in the company.

As a follow to a story last week, where the US put pressure on the Netherlands and ASML to not ship the latest EUV tool to China, the Chinese ambassador is quoted as saying that trade relations between China and the Netherlands would be damaged if ASML is prevented from selling the latest tools to China.

January 17, 2020July 6, 2020

Samsung spend is up but can it offest TSMC slowing?

Samsung spend is up but can it offest TSMC slowing?
by Robert Maire on 01-17-2020 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

Samsung is warming up and spending again
Samsung gave its preliminary report for Q4 and it was well better than prior muted expectations. It doesn’t take long for Samsung’s business units to respond to business trends in either direction and we have already heard of increased spending plans on the part of Samsung.

Samsung has not been shy about spending and has even spent to excess as 2018 bore out. Samsung is equally not shy about cutting spending when the industry slows. We have heard that Samsung has already started to spend even though the recovery in memory is still in early stages and DRAM is well behind NAND in terms of a recovery.

Obviously this is the Wayne Gretzky philosophy of “skate to where the puck is going, not where it has been”. Samsung is trying to get out in front of an expected memory uptick.

This is despite the fact that we have a ton of excess capacity in idled tools sitting around waiting to be turned back on which could easily satisfy increasing demand.

We think that part of Samsung’s spend is more focused on technology rather than pure capacity spend. Samsung has always tried to best its competitors by staying ahead of the cost/technology curve and one way to lead the way out of the memory slow down would be to have an ability to make money at pricing levels that competitors lose money at.

We certainly don’t expect the “drunken sailor” level of spend that Samsung exhibited in 2018 but rather more focused and cautious spend with a technology leaning.

Will Samsung’s spend offset an eventual TSMC decline? As we have previously mentioned, many times, TSMC is a “seasonal” spender focused on getting to the next node in time for Apple’s fall launch of new Iphones. This means that new tools an technology gets ordered and shipped in Q4 and Q1 to iron out the process in Q2 and ramp production in Q3 for the fall launch. We are currently in the midst of a big seasonal spend cycle for TSMC getting its 5NM act together. It is TSMC’s Q4 spend hockey stick that has gotten the equipment industry off the bottom of the cycle.

But all good things come to an end in this most cyclical of industries and TSMC’s spend will likely slow a bit after Q1 as it focuses its efforts on ramping up all that shiny new equipment for 5NM. The real question is will Samsung’s spending ramp offset the expected slowing of TSMC? Probably yes…

We also expect a bit of share shift as memory based spend is obviously very different from logic/foundry spend.

BIS – Little known government agency may prove impactfull

Most people don’t know who or what BIS is. It is a government agency whose acronym BIS stands for “Bureau of Industry & Security”.

With the recent revelation about behind the scenes US pressure on ASML it is clear the government is using an old tool to combat China in the semiconductor industry and that is “national security”.

Its clear that the trade deal has little to no IP protection in it so other means will have to be used to limit the technology flow.

We have suggested that we will likely see more involvement from the government in the form of export licenses/export controls and other methods that are not tariff based.

The mission statement of BIS- “Advance U.S. national security, foreign policy, and economic objectives by ensuring an effective export control and treaty compliance system and promoting continued U.S. strategic technology leadership.”- seems tailor made to be an alternative method to achieve goals that the trade deal didn’t.

We expect to hear more from companies over the next few quarters as the government gets more involved in the regulatory side of trade with China, especially, obviously, in tech.

With think ASML is both the tip of the iceberg and beginning of new phase of government involvement.

While we don’t expect an embargo, we could easily see more scrutiny, more export license issues, denial of export licenses or delays that may impact tech exports to China without an “overt” action.

What will companies report about Q4?

We think companies will generally be more positive. Reports of end product sales have been good. CES 2020 has been very positive and trade concerns have fallen by the wayside.

Memory is getting better. Tech stocks are doing great. Everything is happy. This is all despite the fact that we are going into a seasonally weak Q1.

In general, companies are not likely to “fight the tape” and will likely talk about the improving environment going forward, probably more so because perceived potential risks are reduced.

2019 wasn’t as bad as it otherwise could have been

At one point, chip equipment companies were looking at a 20% down year versus 2017/18 given memory’s cliff dive. TSMC coming through at the end of the year looks to have limited the downside to a lot less, perhaps on down 10% or so.

The downturn lasted about 4 to 5 quarters spanning the second half of 2018 and first 3 quarters or so of 2019. The downturn spanning over two fiscal years rather than focused in one year has mitigated the absolute differential between peak and trough revenues.

Early reports great – Ichor is Punxsutawney Phil that throws no shade

Ichor, one of our favorite sub suppliers to the industry, just pre-announced a great Q4 and an excellent Q1 guide. This obviously bodes very well for both Lam and Applied the two biggest customers of Ichor.

Its not hard to extrapolate that Lam and Applied should have equally great reports – driven by both TSMC and the start of Samsung spend.

Ichor, being a sub-supplier in a cyclical industry is obviously highly levered to the cyclicality and will see even more leverage to the upside than their customers.

The company management has done a great job of acquisitions throughout the cycle and will likely see full benefit in the coming upcycle. It also takes keen management to navigate the downcycle as well as Ichor has, and they have down a great job managing costs and Ichor is clearly a harbinger of good things coming to the industry.

The stocks

Lam and Applied (and of course Ichor) could easily be bought from the Ichor news. We would also suggest MKS and AEIS as well as UCTT. Right now the news out of Q4 wiil be very good with Q1 outlook equally good so we see reduced downside in the near term for most of the stocks.

January 13, 2020July 6, 2020

The Tech Week that was January 6-10 2020

The Tech Week that was January 6-10 2020
by Mark Dyson on 01-13-2020 at 6:00 am
Categories: China, Semiconductor, TSMC

Happy New Year to everyone.. lets hope 2020 is a great year.. The indicators are all pointing in the right direction but it will not take much to derail it if external factors change. Here is my weekly summary of all the important news from the semiconductor industry around the world.

2020 is starting very differently from 2019 with much optimism around. This article in Semiconductor Engineering surveys CEO’s across the industry to get their views on 2020. 5G, AI and big data are all factors that should be big this year and help drive the recovery.

CES was held last week with many new consumer ideas on display. Smart homes was certainly one of the hot topics with smart speakers for the shower, smart frying pans that weight your food and smart cooker hobs that you can control by voice, smart shelves for monitoring your groceries amongst some of the items on display. One item that would certainly be useful in Singapore was a device that instantly cools the object placed in it, like a reverse microwave, it can cool a can of beer in 2minutes. 8K TV’s were on display as were foldable computers, and of course there were lots of robots and AI applications. Here are some articles about the technology on display in the show. An overview from the BBC, the standout gadgets by the Guardian, the key takeaways by the Verge.

The Taiwan foundries ended the year on a high. TSMC hit another record high for the quarter, the second successive quarter it achieved this. Q4 revenue was US$10.5billion, up 8% sequentially. December revenues were down 4% sequentially at US$3.44billion but was up 15% on a year ago.

UMC saw revenues surge in December up 17.4% from a year ago, reporting revenues of US$445million. Q4 revenues were also up 17.4% on a year ago, mainly due to the additional revenues from the taking full control of Mie Fujitsu foundry in Japan.

Specialty foundry Vanguard (VIS) didn’t fair quite so well in Q4, reporting Q4 revenues were down 2.2% on year ago at US$87million.

For the back end assembly test provider ASE reported Q4 revenue up 8.9% YoY at US$2.27billion and up 4.1% sequentially for the ATM group. December revenue was up 2.5% on November with revenue of US$771million, this was up 16% on a year ago.

Market research company IC Insights reported that the pure play foundry market decreased 2% globally in 2019 compared to a year ago. China was the only region to see an increase in pure play foundry market last year growing 6%. Taiwan foundry TSMC reported that approx. 25% of it’s customers were in China.

One of the side effects of trade wars is that it prompts countries to become more self sufficient. As a result of the trade war between South Korea and Japan, South Korea has announced Dupont will invest $28million in South Korea to develop advanced photoresists and other materials by 2021 to allow South Korea to be less dependent on Japan supplies.

Similarly in China, China is pushing to decouple it’s technology from the US as a result of the US-China trade war which has lead to a boom for some Chinese tech companies.

It appears that the US put a lot of pressure on the Netherlands to prevent ASML from delivering a EUV lithography tool to China and to cancel the sale.

Despite the trade war and the ban on Huawei, Huawei still managed to grow it’s revenue in 2019 by 18% to US$121.7billion, though this was lower than originally predicted due to the trade war preventing the company access to source parts. Huawei said that 2020 will be a difficult year and it will not be able to grow as fast and only grow by 3.9%.

It is reported that production was impacted at its Samsung Electronics Hwaseong plant due to a minute long power blackout. It is speculated that the incident caused million of dollars in losses.

January 3, 2020August 31, 2020

Semiconductor Review 2019 into 2020!

Semiconductor Review 2019 into 2020!
by Daniel Nenni on 01-03-2020 at 6:00 am
Categories: China, Semiconductor, TSMC

Semiconductors continue to surge and lead technology sectors all over the world. TSMC has always been my economic bellwether and 2019 was another great year as the TSM share price almost doubled. But it looks like the best is yet to come with TSMC significantly increasing CAPEX to cover 7nm and 5nm demand.

TSMC CEO C.C. Wei increased 2019 CAPEX from $10.5B in 2018 to more than $14B in 2019 with a big Q4 spend. Remember, TSMC builds capacity based on customer orders and not a dart board forecasting. With TSMC winning both the 7nm and 5nm popular vote, 2020 should be another blockbuster CAPEX year to backfill demand.

There are two VERY disruptive semiconductor trends to watch in the next year or three and that is the large systems companies taking control of their silicon (including Google, Facebook, Amazon, Microsoft, etc…) and China also taking control of their silicon.

Apple started it and now all systems companies in competitive markets will follow. It will be interesting to see who the big players are at CES 2020 next week and more importantly how many of them are making their own chips. My bet would be the majority of them including the automakers. It’s not really a fair bet since SemiWiki.com is the leading semiconductor design enablement portal with more than 3.25 million unique views and we get to see who reads what, when, and where they are from.

Why are systems companies dominating semiconductor design? Because they can use prototyping and emulation to get a jump on verification and software development and really tune the silicon to the system. Systems companies are also VERY competitive and can write some VERY big checks and they will not miss tape-outs or product ship dates. This is so un-fabless-like it isn’t even funny. It really is a new semiconductor world order.

Speaking of a new world order, China is also disrupting the semiconductor industry with billions of dollars invested in the “Made in China 2025” semiconductor supply chain initiative.

Think about it, China consumes more than 50% of semiconductor production worldwide and they only produce about 20% of said chips. My guess is 2020 and 2021 will see unprecedented China chip manufacturing growth due to increased memory (DRAM and NAND) manufacturing capacity coming online. Add in the political turmoil motivator and memory hogging mobile, 5G and AI, the Made in China 2025 initiative will get a major boost, my opinion.

I will be in China again this month and am excited to see what’s new. You can Google around all you want but there is nothing like being there.

2019 was also a big year for SemiWiki.com. We unleashed SemiWiki 2.0 in June with many new cloud-based features and more to come. Traffic and member registration is again growing double digits and we are already working on SemiWiki 3.0.

I would truly like to thank all of our bloggers, partners, readers, and registered members for your continued support. SemiWiki has been an exciting 10 year adventure and I’m looking forward to working with you all in the coming years. After spending my entire 35+ year career in semiconductors I can say that without a doubt the best is yet to come, absolutely!

January 1, 2020January 8, 2021

ANSYS, TSMC Document Thermal Reliability Guidelines

ANSYS, TSMC Document Thermal Reliability Guidelines
by Bernard Murphy on 01-01-2020 at 6:00 am
Categories: 5G, Ansys, Inc., EDA, FinFET, Semiconductor, TSMC

Advanced IC technologies, 5nm and 7nm FinFET design and stacked packaging, are enabling massive levels of integration of super-fast circuits. These in turn enable much of the exciting new technology we hear so much about: mobile gaming and ultra-high definition mobile video through enhanced mobile broadband in 5G, which requires support for millimeter wave frequencies; high-speed networking in hyperscalar datacenters through 100G connectivity; blazing fast AI accelerators in those same datacenters; and fusion of multiple sensor sources to build environment-aware intelligence for automotive safety and autonomy, building security, autonomous drones and many more capabilities.

With new technologies we always find new challenges. ANSYS and others have been hearing from chip and system builders supporting these domains that they are seeing increasing post-silicon failures in the devices they are building. These devices are nominally perfectly fine, pass standard testing, but fail in system operation primarily related to voltage, timing and process variations. Tianhao Zhang (Dir. Foundry Relations at ANSYS) says that between what they are hearing from customers and industry reviews, 75% of these product failures can be attributed to thermal or vibration effects.

Thermal also increases cost through need for more advanced cooling, it reduces performance through increased resistance in the interconnect and degraded transistor performance and it increases noise leading to random failures. It also decreases reliability, on chip through electromigration and device aging, and in the package and system through mechanical stress during to warping.

This is not a problem that can be dealt with later. One chip design VP has said that self-heating (related to FinFETs) and thermal analysis are now absolute requirements for automotive and high-performance computing applications. Another noted that compared to planar designs they are now seeing temperature increases in metal of 10 to 20 degrees, and that is making design for reliability much more challenging.

TSMC has been hearing all the same issues and has been increasing the number of checks they require, particularly thermal checks, to offset these types of problem. TSMC has worked closely with ANSYS to prove and document a thermal solution they jointly support. This includes an ANSYS reference flow for transistor, chip and package/3D-IC levels, from 20nm down to 5nm. These can be downloaded from the TSMC portal.

They are also working together on solution guides for specific application flows. For example, ANSYS now provides solution guides for automotive development on 16nm and 7nm. These cover electromigration, thermal and ESD topics. In the thermal analysis section, the document details multiple areas including the flow, and also provides test cases and case studies.

The ANSYS analysis is not based on a simple averaging of thermal effects. They analyze all the way down to the physical implementation of transistors and interconnect systems under representative activity scenarios, to estimate local heating, interconnect heating and heat dissipation. They do this using analytics from RedHawk, together with finite-element analysis applied at the die, stacked die, package and board level. And they’re computing temperature profile by looking at (thermal) conduction, radiation and convection flows, the last of these though detailed fluidics analysis. This is a true bottoms-up multi-physics solution. You can learn more in THIS WEBINAR, presented by Tianhao and Karthik Srinivasan (Sr Prod Mgr at ANSYS).

December 30, 2019September 1, 2024

TSMC, Huawei, the US Government, and China

TSMC, Huawei, the US Government, and China
by Daniel Nenni on 12-30-2019 at 6:00 am
Categories: China, Samsung Foundry, Semiconductor, TSMC
2 Comments

The media is trying to disparage the semiconductor industry again. It’s hard to not take this type of desperate journalism personal. Semiconductor people are the smartest and hardest working people in the world and we deserve better, absolutely.

Morris and Sophie Chang TSMC

TSMC founder sees trade dispute as ‘reality show with no script’ July 2018

The latest media scam is that the US Government is pressuring TSMC about stopping wafer shipments to Huawei (HiSilicon). The Financial Times started it with “US urges Taiwan to curb chip exports to China” and the cut/paste media sites jumped all over it and “made it their own”.

TSMC responded with:

“We did not have any discussion with either the Taiwan or the U.S. governments regarding shipping wafers to HiSilicon, nor have we received any instruction from either government not to make the shipments,” TSMC spokesperson Elizabeth Sun told Caixin in an email, adding that it will continue shipments while complying with trade regulations.

Remember, TSMC has two fabs in China and plenty of room for expansion. The US accounts for 61% of TSMC’s revenue and China is a growing 17%. Taiwan is 8%, Japan 6% and others are 1%. The question is: What would happen if TSMC cut wafer shipments to the US or China? Answer: The end of modern life as we now know it.

Another ignorant quote:

“Last month, a U.S. official informed Taiwanese diplomats that the semiconductors produced by TSMC and then procured by Huawei, were ending up in Chinese missile guidance systems aimed at Taiwan, as per the reporting by Financial Times.”

I can assure you TSMC knows more about what their customers are doing than politicians in any country including Taiwan. There are very few secrets inside the fabless semiconductor ecosystem and TSMC knows more than most. And does it really matter who made what, when, and where in the case of war? It doesn’t matter because there is nothing you can do about it. That ship sailed a long time ago.

Bottom line: TSMC is the new Switzerland and has the full support of the US, Taiwan, and China Governments.

Another interesting headline:

“Samsung is pouring $116 billion towards beating TSMC in the race to 5nm and beyond”

First and foremost, TSMC has already won the race to 5nm and EUV if the finish line is high volume manufacturing versus press releases or “leaked” road maps.

In order for Apple to ship millions of iProducts in Q4 2020 the 5nm EUV process must be frozen by the end of 2019 starting production in Q1 2020. In fact, TSMC recently outlined their 5nm process at IEDM.

I remember when SMIC launched in 2000 and suggested that they would compete with TSMC. It was believable to me because the China Government was strongly behind them and the China consumer market was theirs for the taking. Unfortunately, competing with TSMC proved too hard for SMIC who then resorted to stealing trade secrets. The resulting litigation cost SMIC hundreds of millions of dollars and 10% of their stock.

To say that SMIC is a trailing edge foundry is quite generous. SMIC has just now released a 14nm process four years after TSMC who is now at 5nm with full EUV. SMIC doesn’t even have an EUV machine yet and they may not get one if the current political turmoil is not properly addressed.

According to reports, the SMIC 14nm was co-developed with Qualcomm who also worked with TSMC and Samsung on 14/16nm processes. I’m sure the TSMC and Samsung legal staff already have SMIC 14nm die under review.

GlobalFoundries also had their sites set on competing with TSMC but that never really happened, not even close.

Samsung officially became a pure-play foundry in 2017 when they reorganized all of their logic fabs under Samsung Foundry. Samsung Electronics is Samsung Foundry’s biggest customer of course but they do have a long history of external foundry business. Apple was the big start with the introduction of the iProducts and other big fabless companies (Qualcomm) have followed.

Samsung certainly is a leader in connectivity and IoT now that all Samsung appliances, TVs, and other electronic gadgets have WiFi so they can talk to you throughout the day. You should see the Samsung booth at CES. It’s more of a connected city than a trade show booth but I digress.

Bottom line: While Samsung’s “pouring $116 billion towards beating TSMC” is impressive you have to understand that the TSMC ecosystem of partners and customers have poured trillions of dollars into TSMC staying ahead of all foundry comers, right?

December 16, 2019August 22, 2024

IEDM 2019 – TSMC 5nm Process

IEDM 2019 – TSMC 5nm Process
by Scotten Jones on 12-16-2019 at 10:00 am
Categories: FinFET, GlobalFoundries, Intel Foundry, Samsung Foundry, Semiconductor, TSMC
10 Comments

IEDM is in my opinion the premiere conference for information on state-of-the-art semiconductor processes. In “My Top Three Reasons to Attend IEDM 2019” article I singled out the TSMC 5nm paper as a key reason to attend.

IEDM is one of the best organized conferences I attend and as soon as you pick up your badge you are handed a memory stick with all the conference papers (unlike some other conferences where there are no proceedings). It is very useful to get the papers before seeing them, I typically review a paper, see it presented, and then review it again. I quickly previewed the TSMC paper in advance of the presentation and I have to say I was very disappointed with the lack of real data in the paper, there were no pitches and most of the results graphs were in normalized units. At the 2017 IEDM conference Intel and GLOBALFOUNDRIES (GF) presented their 10nm (7nm foundry equivalent) and 7nm processes respectively and both companies provided critical pitches and electrical results in real units. You can see my previous write up on these papers here.

I would like to take this opportunity to call on TSMC to provide more transparency with respect to their processes.

At the press lunch on Monday many of the IEDM session chairs were available and I asked them about this paper and whether they ever push back on companies to provide more data or reject a paper for lacking enough detail. The answer I got back was yes and in fact they turned down a platform paper from another leading logic company this year for lack of data and said they debated whether to let the TSMC paper in. It is a difficult position for the organizers, this is the kind of headline paper that attracts attendees but at the same time the conference must maintain a standard of quality.

In the balance of this article I will discuss what TSMC disclosed and then try to fill in some of the details they didn’t disclose based on my own investigations. I have read the paper, seen the paper presented, and asked the presenter a question at the end of the presentation and discussed this process with a wide range of industry experts.

TSMC’s disclosures
The key bullet points from the TSMC paper and presentation are:

Industry leading 5nm process.
Full fledged EUV, >10 EUV layers replacing >3 immersion layers each resulting in a reduction in mask count improving cycle time and yield. The paper says >4 immersion layers for each EUV layer but in the presentation the presenter said >3.
High mobility channel FETs.
021µm2 high density SRAM.
~1.84x logic density improvement, ~1.35x SRAM density improvement and ~1.3x analog density improvement.
Gate contact over diffusion, unique diffusion termination, EUV based gate patterning for logic and SRAM.
~15% speed gain or 30% power reduction.
Low resistance and capacitance interconnect with enhanced barrier lines and etch stop layer (ESL) with copper reflow gap fill. The Back-End-Of-Line (BEOL) also features a high resistance resistor for analog use and super high-density Metal-Insulator-Metal (MIM) capacitors
5 and 1.2 volt I/O transistors.
True multi-threshold voltage process with 7 threshold voltages over a >250mv range supported and an extreme low Vt transistor 25% faster than the previous generation. Presumably only around 4Vts are available at a time.
Passed qualification.
High yielding test chip with 256Mb SRAM and CPU/GPU/SOC blocks and D₀ ahead of plan with a faster yield ramp than any previous process. 512Mb SRAM has ~80% average yield and >90% peak yield.
In risk production now with 1^st half 2020 planned high volume production.

Density and pitches
At 7nm Samsung and TSMC have similar process densities. Moving from 7nm to 5nm Samsung has disclosed a 1.33x density improvement and TSMC has disclosed a ~1.84x density improvement. Clearly TSMC will have a far denser process than Samsung and with Intel’s 7nm (5nm foundry equivalent process) not due until 2021, TSMC will have the process density lead in 2020.

In terms of specifics other than an SRAM cell size of 0.021µm2 TSMC didn’t provide any. SRAM density is certainly important for SOC designs where SRAM can often make up over half the device area.

Logic designs are created with standard cells. The height of a standard cell is the Metal 2 Pitch (M2P) multiplied by the track height (TH) and the width is defined by the Contacted Poly Pitch (CPP), cell type and whether the process supports single or double diffusion break. For the TSMC 7FF process M2P is 40nm and the TH is 6. The CPP is specified as 54nm although 57nm is seen in standard cells, however since TSMC stated their density improvement we will assume 54nm as a starting point and the process supports a double diffusion break (DDB). Running these dimensions through the Intel density metric we have discussed before yields 101.85 million transistor/mm².

I have heard that TSMC is going to use a very aggressive 28nm M2P at 5nm and I also believe they will stay with a 6-track cell. A 5-track cell requires Buried Power Rails (BPR) and TSMC did not disclose that as part of the process, I also believe it is too early to see BPR in a process. I also expect this process to support Single Diffusion Break (SDB), SDB was added with the 7FFP version of TSMC’s 7nm process and I believe they will maintain that. The net result is for a 1.84 density improvement CPP is between 49 and 50nm. If I assume 50nm I get 185.46 MTx/mm2 a 1.82x improvement in density.

Figure 1 presents a 7FF versus 5FF process comparison.

Figure 1. TSMC 5FF Process Density.

EUV usage
As I stated previously, the paper mentions a single EUV layer replaces >4 immersion layers although the presentation revised this to >3 immersion layers. The paper and presentation both report 5nm using >10 EUV layers and that would imply >30 immersion layers will be replaced. This is presumably versus the number of immersion layers required if 5FF were done with multi patterning instead of with EUV.

In the article a graph of mask layers is presented with normalized units where 16FFC is 1.00, 10FF ~1.30, 7FF ~1.44 and 5FF ~1.30. I believe TSMC’s 7FF process is 78 masks and the 5FF is 70 masks. When I use my mask estimates for 16FFC, 10FF, 7FF and 5FF I reproduce the graph from the paper nicely.

I also believe TSMC’s 7FFP process has ~5 EUV masks and 5FF will have ~15 EUV masks.

Another interesting EUV comment, I am hearing Samsung has a very high dose for their EUV process for critical layers and I have heard TSMC’s EUV dose is much lower with TSMC a >2x throughput advantage over Samsung> This is also consistent with reports that Samsung is having trouble getting enough wafers through their EUV tools. At another conference I saw an IBM presentation where they discussed developing the 5nm process with Samsung. They said that they turned up the EUV dose until they got good yield and transferred the process to Samsung with the idea that Samsung would then work on reducing the dose. It sounds like the process may have been rushed into production before reducing the EUV dose.

High mobility channels
I have been expecting for some time that Silicon Germanium (SiGe) High Mobility Channels (HMC) will be introduced at 5nm for pFETs.

When I got the TSMC paper and read through it they talk about HMCs plural and even have a figure that says HMC and show both nFET and pFET results, they further show HBC on silicon with no interface buffer layers. The only answer that fits this in my view would be if TSMC had implemented Germanium channels for both nFET and pFET devices, but I thought that was an advance that wasn’t ready yet. If that were the case this would be similar to Intel introducing High K Metal Gates (HKMG) at 45nm or FinFETs at 22nm.

After the TSMC talk I asked the presenter whether the nFET and pFET devices were both HHC or just the nFET or just the pFET. The presenter responded that only one of the device types had HMC although he wouldn’t say which one. I believe it is almost certain that the pFET is a SiGe channel as expected.

Conclusion
In conclusion TSMC has developed a high density 5nm process that will provide the industries highest process density in 2020 and establishes TSMC as the current leader in logic process technology.

December 9, 2019January 10, 2020

As 2019 comes to an end everyone is starting to look at what 2020 holds

As 2019 comes to an end everyone is starting to look at what 2020 holds
by Mark Dyson on 12-09-2019 at 10:00 am
Categories: China, Semiconductor Services, TSMC
3 Comments

At the moment there are many encouraging signs based on the latest data. Let’s hope this trend continues into 2002 and 2020 is the year of recovery of the semiconductor market. However much depends on how the US China trade war pans out. Last week Trump blew hot and cold saying everything from the negotiations were going very well to saying that he thought there may not be an agreement until after the US presidential election next year. The next round of additional US tariffs are due to go in place on December 15th, so hopefully there will be enough progress to delay the imposition of these.

According to IHS Markit, global semiconductor sales dropped 14.2% in the first 3 quarters of 2019 compared to 2018, but there are signs of recovery even in the memory segment which has dragged down the sector so far. Intel retained it’s number 1 position with 16.3% revenue growth in Q3. For the full year IHS Markit estimate sales will recover slightly and only drop 12.4% compared to 2018.

For 2020, they estimate that NAND flash will grow 19%. Strong growth in NAND flash and DRAM is forecast as momentum increases for 5G connectivity, artificial intelligence, deep learning, and virtual reality in mobile, data center and cloud-computer servers, automotive, and industrial markets in 2020.

SEMI reported that October global semiconductor sales rebounded in October with a 2.9% month on month increase with global sales of US$35.6billion, but this was still down 13.1% yoy.

Meanwhile the World Semiconductor Trade Statistics (WSTS) organization projects annual global sales will decrease 12.8 percent in 2019, before the market starts to recover with increases of 5.9 percent in 2020 and 6.3 percent in 2021.

SEMI also published it’s 3rd quarter global semiconductor equipment manufacturers billings data showing a 12% growth over Q2, but still down 6% compared to Q3 2018. Taiwan regained the worlds largest semiconductor market status by growing 21% from Q2, and up 34% from a year ago, buying $3.9billion of equipment. Taiwan was ranked third in semiconductor equipment purchases throughout 2018, behind South Korea and China before taking top slot in Q1, and 2nd in Q2 to China. TSMC capex spending accounted for $3.21billion of the total as it invested to support 7nm, 5nm and 3nm technologies.

In addition TSMC announced it plans to spend US$14~15billion on capital expenditure next year, more than half of this expenditure is going to be spent on expanding its 5nm technology to support 5G technology growth. TSMC see a much stronger than expected demand for 5nm & 7nm due to the rapid deployment of 5G around the world. TSMC also confirmed it is on schedule to start mass production of 3nm in 2022.

Taiwanese foundry UMC has announced that it has released 22nm technology for production.

Taiwan’s manufacturing index hit a 15 month high last month due to strong demand from the electronics sector driven by 5G applications. The PMI increased from 52.7 in October to 54.9 in November with the sub index of new business orders climbed from 52.7 to 61.

In South Korea the outook is not so rosy with export orders of semiconductors decreasing 31% to US$7.4billion in November, the 12th straight month of decline. However market analysts are hopefully of a recovery soon as the Chinese PMI rebounded to 51.8 in November.

Huawei CEO Ren Zhengfei has said it plans to shift it’s US based research centre to Canada. He also said he wants to build some new factory capacity in Europe to build 5G networking equipment.

According to Bloomberg, Chinese semiconductor companies are stockpiling US semiconductor chips in case the trade war worsens and US cuts off access to US technology. In past 3 years Chinese purchases of IC’s has risen strongly, and in the last 2 months imports have been the highest since the start of 2017.

Elsewhere in China Xiaomi and Oppo both announced that they will use Qualcomms latest 5G Snapdragon 865 chip for the flagship smartphones to be released in Q1 next year.

According to the EETimes, ChangXin Memory is emerging as Chinas leading DRAM manufacturer, and is currently running 20,000 wafers per month at its Fab in Hefei. It is currently using 19nm technology to produce LPDDR4, DDR4 8Gbit DRAM products. It has plans to double it’s production in Q2 2020.

In company news, AMS has announced it has succeeded in it’s 2nd bid for Osram having managed to acquire above the required 55% of shares for it’s €41/share bid for the company which values the company at €4.5billion.

Also STMicrolectronics has announced it has acquired the remaining 45% of Swedish silicon carbide wafer manufacturer Norstel AB. Norstel develops and manufactures 150mm silicon carbide (SiC) bare and epitaxial wafers.

December 9, 2019January 13, 2022

Bob Swan says Intel 7nm equals TSMC 5nm!

Bob Swan says Intel 7nm equals TSMC 5nm!
by Daniel Nenni on 12-09-2019 at 6:00 am
Categories: Intel Foundry, Semiconductor, TSMC
20 Comments

Bob Swan is really starting to grow on me. Admittedly, I am generally not a fan of CFOs taking CEO roles at semiconductor companies but thus far Bob is doing a great job. This comes from my outside-looking-in observations and from the people I know inside Intel, absolutely.

Bob did a fireside chat with Credit Suisse at their 23^rd annual technical conference which is now up on the Intel website HERE. It is 51 minutes and definitely worth a listen while sorting laundry or getting a mani pedi.

The media really latched onto Bob’s comments about destroying the Intel idea of keeping the 90% CPU market share and focusing on growing other market segments. Dozens of articles hit the internet by people who have no idea what they are talking about so don’t waste your time.

The most interesting comments to me were in relation to TSMC. According to Bob Swan Intel 7nm is equivalent to TSMC 5nm, which I agree with, I just do not remember an Intel CEO ever saying such a thing. He also said that Intel 5nm will be equivalent to TSMC’s 3nm to which I am not so sure. Making a FinFET to FinFET process equivalency statement is fine but from what I was told Intel will be using Nanosheets at 5nm.

Bob also talks about Intel’s transitions from 22nm to 14nm to 10nm in very simple terms. 22nm to 14nm had a 2.4x density target which as we now know was a very difficult transition. From 14nm to 10nm Intel targeted a 2.7x density target which led to even more manufacturing challenges. Intel 7nm with EUV will be back to a 2.0x scaling target.

Remember, Intel was on a two year process cadence until 14nm. Intel 22nm was launched in 2011, 14nm came 3 years later (2014), and 10nm 5 years after that. Intel 10nm was officially launched in 2019 and Intel 7nm is scheduled for late 2021 which I have no doubt they will hit given the above targets.

TSMC on the other hand delivered 16nm in 2015, 10nm in 2017, and 7nm in 2018. TSMC will deliver 5nm in 2020 and 3nm (also a FinFET based technology) is scheduled for 2022. You can expect 5nm+ to fill in the gap year just as 7nm+ did in 2019. Remember, TSMC is on the Apple iProducts schedule so they have to be in HVM early in the year versus late for Apple to deliver systems in Q4. Intel just has to ship chips.

Bottom line: TSMC is still about a year ahead of Intel on process technology and I do not see that changing anytime soon, my opinion.

I am at IEDM 2019 this week with SemiWiki bloggers Scott Jones and Don Draper (new blogger) so stay tuned. TSMC is giving a paper on 5nm and of course the chatter in the hallways has even more content.

TSMC to Unveil a Leading-Edge 5nm CMOS Technology Platform: TSMC researchers will describe a 5nm CMOS process optimized for both mobile and high-performance computing. It offers nearly twice the logic density (1.84x) and a 15% speed gain or 30% power reduction over the company’s 7nm process. It incorporates extensive use of EUV lithography to replace immersion lithography at key points in the manufacturing process. As a result, the total mask count is reduced vs. the 7nm technology. TSMC’s 5nm platform also features high channel mobility FinFETs and high-density SRAM cells. The SRAM can be optimized for low-power or high-performance applications, and the researchers say the high-density version (0.021µm2) is the highest-density SRAM ever reported. In a test circuit, a PAM4 transmitter (used in highspeed data communications) built with the 5nm CMOS process demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The researchers say high-volume production is targeted for 1H20. (Paper #36.7, “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and HighMobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications,” G. Yeap et al., TSMC)