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Re Energizing Silicon Innovation

Re Energizing Silicon Innovation
by Bernard Murphy on 05-13-2019 at 12:00 pm
Categories: AI, Automotive, Events, Intrinsix, Prototyping, S2C EDA, Synopsys, TSMC
2 Comments

Hardware is roaring back into prominence in technology innovation, from advanced cars to robots, smart homes and smart cities, 5G communication and the burgeoning electronification of industry, medicine and utilities. While software continues to play a role, all of these capabilities depend fundamentally on advances in hardware and particularly novel chip solutions: in sensing, high performance and/or low power compute and communication, AI accelerators and many more functions. Yet amidst this explosive growth, the semiconductor industry has massively consolidated. Fewer and bigger companies do their part to drive innovation but are naturally more risk-averse and more inclined to evolutionary rather than revolutionary advances. Where’s all the real innovation and risk-taking going to come from in this environment?

Thirty to forty years ago, if you could make a convincing case there were plenty of VCs ready to bankroll your venture. As manufacturing costs for advanced processes grew, VCs found the comparably minor capital needs of software ventures much more attractive and steered away from silicon business plans. But designers didn’t stop having ideas or feeling the itch to start new enterprises; they were just stalled by a seemingly insurmountable barrier to entry – raising seed and Series A funding.

Everyone knew this, but Rick Lazansky wanted to do something about it. Rick is a serial entrepreneur, actively involved in the investment community. He believed the industry needed an incubator to help silicon innovators with good ideas get past this hurdle. Incubators and accelerators are not new concepts but his creation, Silicon Catalyst, makes particular allowance for the special needs of this domain. They provide a pool of seed investors, two years of design tool access, manufacturing and test, access to a wide range of advisors with lots of industry experience and access to a premium group of strategic partners looking for innovations they need. You’ll still have to raise some of your own investment to prove you have skin in the game, but the barrier is now much less daunting.

Before you quit your job, get a second mortgage on the house and tell your significant other that the family will be living with your parents if your venture doesn’t work out, remember that as with any incubator, you’re going to have to do some work to be accepted; I’ll get to that. But first some more detail on that buffet of goodies to which you’ll have access if you cross that hurdle.

Your immediate concern is probably how you manage EDA, IP and design services, MPW, packaging and test costs. Silicon Catalyst has assembled a group of 25+ in-kind partners who will provide 2 years of free or significantly-discounted access to their capabilities and services from the time your clock starts. These include Synopsys for design tools, S2C for emulation, SiFive and Silvaco for IP, TSMC MPWs for prototype manufacturing, Advantest and EAG for test, Mathworks, AWS, Instrinsix, MEMS design and foundry solutions, patent lawyers, even a CFO app – and many more. They cover pretty much everything you’re going to need to create that prototype. These partners see value in this access because they see the portfolio companies as potential new customers.

There are multiple strategic ecosystem partners, including Bosch, On Semiconductor, Soitec and TI Semiconductor; I met the Bosch representative at a recent event. Strategic partners pay close attention to the portfolio companies working in their areas of interest. Bosch knows that that interesting startups have neither bandwidth nor the nerve to approach a company of their size. By being a strategic partner, they can interact with promising ventures very early on during the screening process and react quickly if they see a fit. Others see opportunities in hot areas such as photonics where they see potential to build further demand for their technology.

Among advisors, full disclosure – I’m now an advisor, but they have some really good people too. Just a small sample includes Dave French (past CEO of Cirrus Logic and EVP at NXP), John East (past CEO of Actel Semi), Misha Burich (past CTO and VP at Altera) and Mark Ross, (ex-Cypress Semi EVP & CTO). There are 120+ advisors aligned with Silicon Catalyst, with skills ranging from globalization to manufacturing development, angel investments, MEMS – it’s all on the website.

Investors include Rick himself, Jim Hogan and many of the advisors. There are options for seed money to come from individual investors, also from an ecosystem investor group to which multiple angels can contribute. Angels particularly are attracted by the reduced risk over personal investing. In the personal approach there’s a lot of risk and a lot of work for an investor to decide where and how much they should invest. Investing together with others in in a pre-screened group of portfolio companies can look like a pretty attractive proposition. The Silicon Catalyst approach reduces risk all round – for portfolio startups, investors, in-kind and strategic partners.

Silicon Catalyst looks at opportunities from lots of domains and geographies, spanning pre-seed to post-Series-A chip startups. Existing portfolio companies are in analog-based AI, communications, ultra-low power design and others, some in Silicon Valley but also in Canada, Korea and Singapore. From their founding in 2015, they’ve connected to over 250 startups, receiving applications from Europe, India and other locations. There’s now a joint venture in Chengdu, China focused on the power semiconductor ventures and they’re exploring the possibility of another joint venture to assist startups in Israel.


So what’s the catch? Applicants are screened through a rigorous review process; historically, only one out ten makes it through to becoming a portfolio company. That’s so all those supporting individuals and organizations feel they are getting value for their investments in the domains that most interest them. Nick Kepler (COO) told me that even though selection is obviously rigorous, he wants to make sure that each applicant gets value out of the process even if they aren’t selected. Worth remembering even if you’re not sure you are ready. This could be a way to find out what you have to do to tune up your game.

Silicon Catalyst has around 20 companies in the portfolio, they raised their own investment round last year and they’re planning to get to several hundred companies in the portfolio over the next 7-10 years. As a measure of success, they already have portfolio companies who have graduated from the incubator to Series A funding.

OK, I’m obviously biased. But c’mon – when did you last see an idea this exciting for any would-be silicon entrepreneur? If you want to learn more, first click HERE. Also know that upcoming events for their ecosystem members include a Portfolio Company Update (what others call “Demo Day”) and their Semi Industry Forum, both at the end of May. And for you entrepreneurs, the deadline to apply for the Fall Screening Event is in July. Check out their website to learn about the application process.

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TSMC and Samsung 5nm Comparison

TSMC and Samsung 5nm Comparison
by Scotten Jones on 05-03-2019 at 7:00 am
Categories: Foundries, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
9 Comments

Samsung and TSMC have both made recent disclosures about their 5nm process and I though it would be a good time to look at what we know about them and compare the two processes.

A lot of what has been announced about 5nm is in comparison to 7nm so we will first review 7nm.

7nm
Figure 1 compares Samsung’s 7LPP process to TSMC’s 7FF and 7FFP processes. The rows in the table are:

  • Company name
  • Process name
  • M2P – metal 2 pitch, this is chosen because M2P is used to determine cell height
  • Tracks – the number of metal two pitches in the cell height
  • Cell height – the M2P x Tracks
  • CPP – contacted polysilicon pitch
  • DDB/SDB – double diffusion break (DDB) or single diffusion break (SDB). DDB requires an extra CPP in width at the edge of a standard cell
  • Transistor density – this is uses the method popularized by Intel that I have written before where two input NAND cell size and scanned flip flop cell sizes are weighted to give a transistors per millimeter metric
  • Layers – this is the number of EUV layers over the total number of layers for the process
  • Relative cost – using Samsung’s 7LPP cost as the baseline we compare the normalized cost of each process to 7PP. The cost values were calculated using the IC Knowledge – Strategic Cost Model – 2019 – revision 01 versions for a new 40,000 wafers per month wafer fabs in either South Korea for Samsung or Taiwan for TSMC
    Figure 1. 7nm comparison

     

    Looking at figure 1 it is interesting to note that Samsung’s 7LPP process is less dense than either of TSMC’s processes in spite of using EUV and having the smallest M2P. TSMC more than makes up for Samsung’s tighter pitch with a smaller track height and then for 7FFP a SDB. For TSMC 7FF without EUV moving to 7FFP with EUV reduces the mask count and adds SDB improving the density by 18%.

    Now that we have a solid view of 7nm we are ready to look forward to 5nm:

    5nm
    Both Samsung and TSMC have started taking orders for 5nm with risk production this year and high-volume production next year. We expect both companies to employ more EUV layers at 5nm with 12 for Samsung and 14 for TSMC.

    Samsung has said their 5nm process offers a 25% density improvement over 7nm with a 10% performance boost or 20% lower power consumption. My understanding is the difference between 7LPP and 5LPE for Samsung is a 6-track cell height and SDB. This results in a 1.33x density improvement.

    This contrasts with TSMC who announced a 1.8x density improvement and a 15% performance improvement or 30% lower power. I recently saw another analyst claim that Samsung and TSMC would have similar density at 5nm, that one really left me scratching my head given that the two companies have similar 7nm density and TSMC has announced a much larger density improvement than Samsung. My belief is that TSMC will have a significant density advantage over Samsung at 5nm.

    Figure 2 summarizes the two processes using the same metrics as figure 1 with the addition of a density improvement versus 5nm row.

    Figure 2. 5nm comparison

     

    From figure 2 you can see that we expect TSMC to have a 1.37x density advantage over Samsung with a lower wafer cost!

    Another interesting item in this table is TSMC reaching 30nm for M2P. We have heard they are being aggressive on M2P with numbers as low as 28nm mentioned. We assumed 30nm as a slight relaxation from the 28nm number to produce the 1.8x density improvement, TSMC had at one time said 5nm would have a 1.9x density improvement.

    Conclusion
    We believe TSMC’s 5nm process will significantly outperform Samsung’s 5nm process in all key metrics and represent the highest density logic process in the world when it ramps into production next year.

    For more information on TSMC’s leading edge logic processes I recommend Tom Dillinger’s excellent summary of TSMC’s technology forum available here.

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TSMC Technology Symposium Review Part II

TSMC Technology Symposium Review Part II
by Tom Dillinger on 04-30-2019 at 10:00 am
Categories: Events, Foundries, TSMC
6 Comments

TSMC recently held their annual Technology Symposium in Santa Clara. Part 1 of this article focused on the semiconductor process highlights. This part reviews the advanced packaging technologies presented at the symposium.

TSMC has clearly made a transition from a “pure” wafer-level foundry to a supplier of complex integrated system modules – or according to C.C. Wei, CEO, TSMC is a leading source for “nano-mass production innovations”. (Taiwan News, 4/23/19) This is the outcome of years of R&D investment – for example, see the discussion on 3D stacking in the “SoIC” section below.

Dr. Doug Yu, VP, Integrated Interconnect and Package R&D provided a detailed update. Dr. Yu classified the package technologies into unique categories – “front-end” 3D chip integration (SoIC) and “back-end” packaging advances (CoWoS, InFO). Additionally, he addressed the progress in pad pitch and Cu pillar/SnAg bump lithography, specifically mentioning the automotive grade reliability requirements.

Here’s a brief recap of the TSMC advanced packaging technology status.

Bumping
TSMC continues to advance bump technology, with 60-80um bump pitch achievable (for smaller die).

CoWoS
The initial TSMC 2.5D packaging offering was chip-on-wafer-on-substrate (CoWoS), which has enabled very high-performance system integration by bringing memory “closer to the processor”.

  • >50 customer products
  • TSMC is developing “standardized” configurations – e.g., 1 SoC with 2 or 4 HBMs, evolving to >2 SoCs with 8 HBM2Es (96GB @ 2.5TB/sec – wow.)

Correspondingly, TSMC will be expanding the maximum 2.5D interposer footprint from a max of 1X reticle (~50×50) to 3X (~85×85), with a 150um bump pitch.

  • The silicon interposer supports 5 metal layers and a (new) deep trench capacitor – see the figure below.

InFO
TSMC continues to evolve the Integrated FanOut (InFO) package offerings. Recall that InFO is a means of integrating (multiple) die using a “reconstituted wafer” molding compound to provide the package substrate for RDL patterning. InFO builds upon the traditional small-package WLCSP technology to enable (large area) redistribution interconnect and high bump count – see the figure below.

InFO-PoP supports stacking of a logic die and a DRAM die on top of the base, using through-InFO-vias (TIV) to connect the DRAM to the metal layers. InFO-PoP development has focused on improving the pitch and aspect ratio (vertical-to-diameter) of the TIVs.

InFO-on-Substrate offerings attach a (multi-die) InFO module to a (large area) substrate, leveraging the multiple reticle stitching technology developed for CoWoS.

SoIC (“front-end” 3D integration)
The big packaging announcement at the symposium was the introduction of the “front-end” 3D die stacking topology, denoted as SoIC (System-on-Integrated Chips).

SoIC is a “bumpless” interconnect method between multiple die. As depicted in the figure below (from an early R&D paper from TSMC), Cu pads from a base die and exposed Cu “nails” from the (thinned) top die utilize thermo-compression bonding to provide the electrical connection. (An appropriate underfill material is present at the die-to-die interface, as well.)

  • Through-silicon vias in the die provide connectivity, with a very tight pitch.
  • Both face-to-face and face-to-back die connectivity are supported. The “known good” stacked die may be different sizes, with multiple die on a stacked layer.
  • TSMC showed a mock-up of a 3-high vertical SoIC stack.
  • EDA enablement is available: physical design (DRC, netlisting/LVS), parasitic extraction, timing, IR/EM analysis, signal integrity/power integrity analysis, thermal/materials stress analysis.
  • The qualification target for the SoIC package offering is YE’2019. (My understanding from a separate TSMC announcement is SoIC volume availability will be in 2021.)

Dr. Yu also indicated, “The front-end SoIC module will be able to be integrated as part of a back-end 2.5D offering, as well.”

Summary
Both 2.5D and InFO “back-end” package offerings continue to evolve.

Yet, for me the highlight was the introduction of the tight-pitch, Cu compression-bonded full-3D stacked die of the SoIC topology. The available circuit density (per mm**3) will be very appealing. The challenges to leverage this technology will be considerable, though, from system architecture partitioning to complex electrical/thermal/mechanical analysis across the stacked die interfaces.

Moore’s Law is definitely alive-and-well, although it will require 3D glasses. 😀

-chipguy

Also read: 2019 TSMC Technology Symposium Review Part I

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2019 TSMC Technology Symposium Review Part I

2019 TSMC Technology Symposium Review Part I
by Tom Dillinger on 04-30-2019 at 7:00 am
Categories: Events, Foundries, TSMC
5 Comments

Each year, TSMC conducts two major customer events worldwide – the TSMC Technology Symposium in the Spring and the TSMC Open Innovation Platform Ecosystem Forum in the Fall. The Technology Symposium event was recently held in Santa Clara, CA, providing an extensive update on the status of advanced semiconductor and packaging technology development. This article briefly reviews the highlights of the semiconductor process presentations – a subsequent article will review the advanced packaging announcements.

First, some general items that might be of interest:

Longevity
TSMC was founded in 1987, and has been holding annual Technology Symposium events since 1994 – this was the 25th anniversary (which was highlighted prevalently throughout the Santa Clara Convention Center). “The first Silicon Valley symposium had less than 100 attendees – now, the attendance exceeds 2000.”, according to Dave Keller, President and CEO of TSMC North America.

Best Quote of the Day
Dr. Cheng-Ming Lin, Director, Automotive Business Development, describes the unique requirements of TSMC’s automotive customers, specifically with regards to continuity of supply over a much longer product lifetime. He indicated,

“Our commitment to legacy processes is unwavering. We have never closed a fab or shut down a process technology.” (Wow.)

Best Quip of the Day
Dr. Y.-J. Mii, Senior Vice President of Research and Development / Technology Development , highlighted three eras of process technology development, as depicted in the figure below from his presentation.

In the first phase, Dennard scaling refers to the goal of scaling FEOL linear lithographic dimensions by a factor of “s” (s < 1) in successive process nodes, achieving an improvement of (1 / s**2) in circuit density, measured as gates / mm**2. The next phase focused on material improvements, and the current phase centers on design-technology co-optimization – more on that shortly.

In a subsequent presentation at the symposium, Dr. Doug Yu, VP, Integrated Interconnect and Packaging R&D, described how advanced packaging technology has also been focused on scaling, albeit for a shorter duration. “For over 10 years, packages have also offered two-dimensional improvements to redistribution layer (RDL) and bump pitch lithography. With the multi-die, 3D vertical stacking package technology we’re describing today – specifically, TSMC’s SoIC offering – we are providing vast improvements in circuit density. S is equal to zero. Or, in other words, infinite scaling.” 😀 (Indeed, it is easy to foresee product technologies starting to use the metric “gates / mm**3” .)

Here is a brief recap of the TSMC advanced process technology status.

N7/N7+
TSMC announced the N7 and N7+ process nodes at the symposium two years ago. (link)

N7 is the “baseline” FinFET process, whereas N7+ offers improved circuit density with the introduction of EUV lithography for selected FEOL layers. The transition of design IP from N7 to N7+ necessitates re-implementation, to achieve a 1.2X logic gate density improvement. Key highlights include:

 

  • N7 is in production, with over 100 new tapeouts (NTOs) expected in 2019
  • Key IP introduction: 112Gbps PAM4 SerDes
  • N7+ is benefitting from improvements in sustained EUV output power (~280W) and uptime (~85%). “Although we anticipate further improvements in power and uptime, these measures are sufficient to proceed to N7+ volume ramp.”, TSMC said.
  • TSMC has focused on defect density (D0) reduction for N7. “The D0 improvement ramp has been faster than previous nodes, at a comparable interval after initial production volume ramp.”, according to TSMC.
  • TSMC illustrated a dichotomy in N7 die sizes – mobile customers at <100 mm**2, and HPC customers at >300 mm**2.
  • To my recollection, for the first time TSMC also indicated they are tracking D0 specifically for “large chips”, and reported a comparable reduction learning for large designs as for other N7 products.
  • N7+ will enter volume ramp in 2H2019, and is demonstrating comparable D0 defect rates as N7.

“Making 5G a Reality”
TSMC invited Jim Thompson, CTO, Qualcomm, to provide his perspective on N7 – a very enlightening presentation:

  • “N7 is the enabler for the 5G launch, as demonstrated in our latest Snapdragon 855 release.”
  • “5G MIMO with 256 antenna elements supports 64 simultaneous digital streams – that’s 16 users each receiving 4 data streams to a single phone.”
  • “Antenna design is indeed extremely crucial for 5G, to overcome path loss and signal blockage. There are new, innovative antenna implementations being pursued – in the end, it’s just math, although complex math for sure.”
  • “There’s certainly lots of skepticism about the adoption rate of 5G. Yet 5G is moving much faster than 4G did – at a comparable point in the rollout schedule, there were only 5 operators and 3 OEM devices supporting 4G, mostly in the US and South Korea. Currently, there are over 20 operators and over 20 OEM devices focused on 5G deployment, including Europe, China, Japan, and Southeast Asia.”
  • “And, don’t overlook the deployment of 5G in applications other than consumer phones, such as ‘wireless factory automation’. Communication to/from industrial robots requires high bandwidth, low latency, and extremely high availability. Consider the opportunities for manufacturing flexibility in a wire-free environment, enabled by 5G.”

N6
TSMC introduced a new node offering, denoted as N6. This node has some very unique characteristics:

  • design rule compatible with N7 (e.g., 57mm M1 pitch, same as N7)
  • IP models compatible with N7
  • incorporates EUV lithography for limited FEOL layers – “1 more EUV layer than N7+, leveraging the learning from both N7+ and N5”
  • tighter process control, faster cycle time than N7
  • same EDA reference flows, fill algorithms, etc. as N7
  • N7 designs could simply “re-tapeout” (RTO) to N6 for improved yield with EUV mask lithography
  • or, N7 designs could submit a new tapeout (NTO) by re-implementing logic blocks using an N6 standard cell library (H240) that leverages a “common PODE” (CPODE) device between cells for an ~18% improvement in logic block density
  • risk production in 1Q’20 (a 13 level metal interconnect stack was illustrated)
  • although design rule compatible with N7, N6 also introduces a very unique feature – “M0 routing”

The figure below illustrates a “typical” FinFET device layout, with M0 solely used as a local interconnect, to connect the source or drain nodes of a multi-fin device and used within the cell to connect common nFET and pFET schematic nodes.


I need to ponder a bit more on the opportunity use M0 as a routing layer – TSMC indicated that EDA router support for this feature is still being qualified.

N6 strikes me as a continuation of TSMC’s introduction of a “half node” process roadmap, as depicted below.


A half-node process is both an engineering-driven and business-driven decision to provide a low-risk design migration path, to offer a cost-reduced option to an existing N7 design as a “mid-life kicker”.

The introduction of N6 also highlights an issue that will become increasingly problematic. The migration of a design integrating external IP is dependent upon the engineering and financial resources of the IP provider to develop, release (on a testsite shuttle), characterize, and qualify the IP on a new node on a suitable schedule. N6 offers an opportunity to introduce a kicker without that external IP release constraint.

N5
The process node N5 incorporates additional EUV lithography, to reduce the mask count for layers that would otherwise require extensive multipatterning.

 

  • risk production started in March’19, high volume ramp in 2Q’20 at the recently completed Gigafab 18 in Tainan (phase 1 equipment installation completed in March’19)
  • intended to support both mobile and high-performance computing “platform” customers; high-performance applications will want to utilize a new “extra low Vt”(ELVT) device
  • 1.5V or 1.2V I/O device support
  • an N5P (“plus”) offering is planned, with a +7% performance boost at constant power, or ~15% power reduction at constant perf over N5 (one year after N5)
  • N5 will utilize a high-mobility (Ge) device channel

Advanced Materials Engineering
In addition to the N5 introduction of a high mobility channel, TSMC highlighted additional materials and device engineering updates:

  • super high-density MIM offering (N5), with 2X ff/um**2 and 2X insertion density
  • new low-K dielectric materials
  • metal Reactive Ion Etching (RIE), replacing Cu damascene for metal pitch < 30um
  • a graphene “cap” to reduce Cu interconnect resistivity

An improved local MIM capacitance will help to address the increased current from the higher gate density. TSMC indicated an expected single-digit % performance increase could be realized for high-performance (high switching activity) designs.

Nodes 16FFC and 12FFC both received device engineering improvements:

  • 16FFC+ : +10% perf @ constant power, +20% power @ constant perf over 16FFC
  • 12FFC+ : +7% perf @ constant power, +15% power @ constant perf over 12FFC

NTO’s for these nodes will be accepted in 3Q’19.

TSMC also briefly highlighted ongoing R&D activities in materials research for future nodes – e.g., Ge nanowire/nanoslab device channels, 2D semiconductor materials (ZrSe2, MoSe2) – see the figure below (Source: TSMC).

Manufacturing Excellence
Dr. J.K. Wang, SVP, Fab Operations, provided a detailed discussion of the ongoing efforts to reduce DPPM and sustain “manufacturing excellence”. Of specific note were the steps taken to address the demanding reliability requirements of automotive customers. Highlights of Dr. Wang’s presentation included:

“Since the introduction of the N16 node, we have accelerated the manufacturing capacity ramp for each node in the first 6 months at an ever-increasing rate. The N7 capacity in 2019 will exceed 1M 12” wafers per year. The N10/N7 capacity ramp has tripled since 2017, as phases 5 through 7 of Gigafab 15 have come online.”

“We have implemented aggressive statistical process control (measured on control wafer sites) for early detection, stop, and fix of process variations – e.g., upward/downward shifts in baseline measures, a variance shift, mismatch among tools. We have established 2D wafer profile measurement criteria, and in-line monitoring and comparison to an “acceptance” profile across each wafer.”

“The DDM reduction rate on N7 has been the fastest of any node.”

“For automotive customers, we have implemented unique measures to achieve the demanding DPPM requirements. We will ink out good die in a bad zone. And, there are SPC criteria for a maverick lot, which will be scrapped.”

“We will support product-specific upper spec limit and lower spec limit criteria. We will either scrap an out-of-spec limit wafer, or hold the entire lot for the customer’s risk assessment.” (See the figures below. Source: TSMC)



Automotive Platform
TSMC has developed an approach toward process development and design enablement features focused on four platforms – mobile, HPC, IoT, and automotive. Dr. Cheng-Ming Lin, Director, Automotive Business Unit, provided an update on the platform, and the unique characteristics of automotive customers.

Growth in semi content
Dr. Lin indicated, “Automotive systems will require both advanced logic technologies for ADAS, such as N16FFC, and advanced RF technologies for V2X communications. Although the CAGR for cars from now to 2022 is expected to be only ~1.8%, the CAGR for the semiconductor content will be 6.9%.”

He continued, “The L1/L2 feature adoption will reach ~30%, with additional MCU’s applied to safety, connectivity, and EV/hybrid EV features. There will be ~30-40 MCU’s per vehicle. “ (In his charts, the forecast for L3/L4/L5 adoption is ~0.3% in 2020, and 2.5% in 2025.)

“The adoption rate for the digital dashboard cockpit visualization system will also increase, driving further semiconductor growth – 0.2% in 2018 to 11% in 2025.”

L2+
The levels of support for automated driver assistance and ultimately autonomous driving have been defined by SAE International as “Level 1 through Level 5”. Perhaps in recognition of the difficulties in achieving L3 through L5, a new “L2+” level has been proposed (albeit outside of SAE), with additional camera and decision support features.

“An L2+ car would typically integrate 6 cameras, 4 short-range radar systems, and 1 long-range radar unit, requiring in excess of 50GFLOPS graphics processing and >10K DMIPS navigational processing throughput.”

N16FFC, and then N7
The 16FFC platform has been qualified for automotive environment applications – e.g., SPICE and aging models, foundation IP characterization, non-volatile memory, interface IP. The N7 platform will be (AEC-Q100 and ASIL-B) qualified in 2020. “Automotive customers tend to lag consumer adoption by ~2-3 years, to leverage DPPM learning – although that interval is diminishing. We anticipate aggressive N7 automotive adoption in 2021.”,Dr. Lin indicated.

“The TSMC RF CMOS offerings will be used for SRR, LRR, and Lidar. The 16FFC-RF-Enhanced process will be qualified for automotive platforms in 2Q’20.”

IoT Platform
The TSMC IoT platform is laser-focused on low-cost, low (active) power dissipation, and low leakage (standby) power dissipation. Dr. Simon Wang, Director, IoT Business Development, provided the following update:

Process Roadmap

  • 55ULP, 40ULP (w/RRAM): 0.75V/0.7V
  • 22ULP, 22ULL: 0.6V
  • 12FFC+_ULL: 0.5V (target)
  • introduction of new devices for the 22ULL node: EHVT device, ultra-low leakage SRAM

The 22ULL SRAM is a “dual VDD rail” design, with separate logic (0.6V, SVT + HVT) and bitcell VDD_min (0.8V) values for optimum standby power.

The 22ULL node also get an MRAM option for non-volatile memory.

Note that a new methodology will be applied for static timing analysis for low VDD design. The stage-based OCV (derating multiplier) cell delay calculation will transition to sign-off using the Liberty Variation Format (LVF).

The next generation IoT node will be 12FFC+_ULL, with risk production in 2Q’20. (with low VDD standard cells at SVT, 0.5V VDD).

RF
TSMC emphasized the process development focus for RF technologies, as part of the growth in both 5G and automotive applications. Dr. Jay Sun, Director, RF and Analog Business Development provided the following highlights:

  • For RF system transceivers, 22ULP/ULL-RF is the mainstream node. For higher-end applications, 16FFC-RF is appropriate, followed by N7-RF in 2H’20.
  • Significant device R&D is being made to enhance the device ft and fmax for these nodes – look for 16FFC-RF-Enhanced in 2020 (fmax > 380GHz) and N7-RF-Enhanced in 2021.
  • New top-level BEOL stack options are available with ‘elevated’ ultra thick metal for inductors with improved Q.
  • For sub-6GHz RF front-end design, TSMC is introducing N40SOI in 2019 – the transition from 0.18um SOI to 0.13um SOI to N40SOI will offer devices with vastly improved ft and fmax.

Summary
There was a conjecture/joke going around a couple of years ago, suggesting that “only 7 customers will be able to afford to pursue 7nm designs, and only 5 customers at 5nm”.

Clearly, the momentum behind N7/N6 and N5 across mobile communication, HPC, and automotive (L1-L5) applications dispels that idea. TSMC is investing significantly in enabling these nodes through DTCO, leveraging significant progress in EUV lithography and the introduction of new materials.

Part 2 of this article will review the advanced packaging technologies presented at the TSMC Technology Symposium.

-chipguy

Also read: TSMC Technology Symposium Review Part II

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A Quick TSMC 2019 Tech Symposium Overview

A Quick TSMC 2019 Tech Symposium Overview
by Daniel Nenni on 04-26-2019 at 7:00 am
Categories: Events, FinFET, Foundries, TSMC
3 Comments

This year TSMC did a FinFET victory lap with the success of 16nm, 12nm, 10nm, and 7nm. It really is well deserved. Even though TSMC credits the ecosystem and customers, I credit TSMC and their relationship with Apple since it has pushed us all much harder than ever before. TSMC CEO C.C. Wei summed it up nicely in his keynote: Innovation, collaboration, and hard work.

Tom Dillinger also attended and he will be writing in more detail next week. Tom has been busy of late. He just finished his second textbook on VLSI Design Methodology Development for Prentice Hall. Remember, Tom started the FinFET discussion on SemiWiki in 2012 so you can bet FinFETs will be mentioned a time or two.

Here is an outline of what Tom will be writing about next week so stay tuned:

Advanced Technology Development and Materials Engineering:
1) N7/N7+ update
highlights: “Making 5G a Reality” — N7 as a technology enabler; D0 defect density improvement; 112Gbps PAM4 SerDes IP

2) N6 update
highlights: PPA comparisons to N7; ease of RTO/NTO migration from N7; new M0 routing (very unique!)

3) N5 update
highlights: schedule; D0 ramp; PPA comparisons to N7; “designed from the start for both mobile and HPC platforms”

4) Advanced process development / materials engineering
highlights: additional Vt devices for HPC in N5 and ULL/ULP technologies; high mobility (Ge) channel device; metal RIE (replacing damascene patterning); new metallization materials (graphene cap on Cu); future research into 2D semiconductor materials

5) Manufacturing excellence
highlights: focus on in-line process monitoring; maverick lot identification; “ink out good die in a bad zone” (very unique!); Continuous Process Improvement focused on wafer edge (very unique!); product-specific UpperSpecLimit + LowerSpecLimit statistical process control (also very unique!)

6) Roadmap for automotive platform
highlights: new “L2+” automotive grade introduced; focus on DPPM reduction; MCU’s in a vehicle transitioning from eFlash to MRAM memory offering

7) Roadmap for IoT platform
highlights: new eHVT device; unique analog device process engineering; new “dual-rail VDD” SRAM offerings (aggressive SRAM_Vmin scaling); MRAM roadmap

8) RF process development focus
highlights: device engineering to improve ft and fmax (in several processes), new thick metal to improve inductor Q factor; device model characterization

Although the specialty technologies presentation was very interesting, there’s probably not enough room in the article to cover MEMS, CIS (at near infrared wavelengths), etc.

“Front-End” and “Back-End” Advanced Packaging:
1) SoIC
highlights: diverse die size and stacking options (e.g., face-to-face and face-to-back bonding)

2) CoWoS
highlights: reticle size roadmap, embedded deep trench caps (DTC) in Silicon interposer

3) InFO
highlights: InFO_PoP through InFO via (TIV) scaling; InFO without substrate (2020)
4) 3DIC ecosystem support

History is always a part of semiconductor symposiums because semiconductors really have come a long way fueled by a series of technological disruptions. When I went away to college my beautiful girlfriend (wife) used to write letters to me everyday and call me on the weekends. My parents and grandparents had similar experiences. Shortly after we married, PCs and the internet landed on our desks and we emailed and Usenet-ed our way around the world. Then came smartphones and social media, probably the biggest disruption of them all. Phones are now in our hands and faces more than ever before but that is going to change.

The next disruption will be fueled by 5G and AI which is just now beginning. If you think semiconductors are important today just wait another ten years because you will not be able to survive without them, absolutely.

TSMC and the semiconductor industry have been living a very mobile life since PCs and phones left our desks. Moving forward, AI enabled edge devices will continue to be a semiconductor industry driver but the real upside for the foundry business will be getting the many zettabytes of data into the cloud and processed. Today Intel CPUs and GPUs dominate the cloud. Tomorrow it will be custom AI processors built by the cloud companies themselves in close partnership with the fabless semiconductor ecosystem and that means TSMC.

From writing letters to “real-time thought processing” in one lifetime, simply amazing.

Also read: 2019 TSMC Technology Symposium Review Part I

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TSMC Q1 2019 Earnings Call Discussion!

TSMC Q1 2019 Earnings Call Discussion!
by Daniel Nenni on 04-19-2019 at 7:00 am
Categories: Events, Foundries, TSMC
18 Comments

It’s no coincidence that the TSMC Symposium is right after the Q1 earnings call. This will allow TSMC to talk more freely and they certainly will, my opinion. It is a very interesting time in the semiconductor industry and TSMC, being the bellwether, can tell us what will happen the rest of the year and give us some 2020 insights.

TSMC CEO C.C. Wei again led the call with a prepared statement. This time I will paste the entire statement (minus the packaging stuff) with my embedded comments.

  • Thank you, Lora. Good afternoon, ladies and gentlemen. Let me start with our near-term demand and inventory. We concluded our first quarter with revenue of TWD 280.7 billion or USD 7.1 billion, in line with our revised guidance. Our business in the first quarter was impacted by three factors: first, the overall global economic condition, which dampened the end market demand; second, customers are ongoing inventory adjustment; and third, the high-end mobile product seasonality. Meanwhile, the net effect from the photoresist defect material incident also impact our first quarter revenue by about 3.5%.

My question here is: Who is liable for this defect? Is the supplier being held accountable? Accounts of this incident from South Korea painted TSMC as negligent which I have found to be fake news.

  • Moving into second quarter this year. While the economical factor and mobile product seasonality still linger, we believe we may have passed the pattern of the cycle of our business as we are seeing customers’ demand stabilizing. Based upon customer indications for their business and wafer loading in second quarter, we also expect our customers’ overall inventory to be substantially reduced and approach the seasonal level around the middle of this year.

Personally, I feel the second quarter will be stronger than expected based on 2018 year end CEO comments. It is better to under predict than over predict and I believe that is what is happening here. Let’s not forget the Q1 2019 semiconductor guidance we previously published:

  • In the second half of this year, TSMC’s business will be supported by this year’s inventory base as well as strong demand from our industry-leading 7-nanometer technology, which support high-end smartphone new product launches, initial 5G deployment and HPC-related applications. For the whole year of 2019, we forecast the overall semiconductor market is good in memory as well as foundry growth to both be flattish. For TSMC, we reiterate that we expect to grow slightly in 2019.

To me this is low single digits but closer to 5% than 1%. Here are the previously published analyst forecasts for 2019:

  • Now let me update the photoresist material incident. On February 15, in order to ensure quality of wafer delivery, TSMC announced it will scrap a large number of wafers as a result of a batch of bad photoresist material from a chemical supplier. This batch of photoresist contain a foreign polymer that created a desirable – undesirable effect and resulted in yield deviation on 12-and 16-nanometer wafers at Fab 14B.
  • We have since taken corrective action to enhance our defenses and minimize future risk. Our actions including the following: improved TSMC’s own in-house incoming material, conforming test and controls; upgrade control and methodology with all suppliers for incoming material quality certification; establish robust in-line and off-line monitoring process to prevent defect escape.

TSMC does not point fingers but again I would like to know more about this event.

  • Now I will talk about our N5 status. Our N5 technology development is well on track. N5 has entered risk production in first quarter, and we expect customer tape-outs starting this quarter and volume production ramp in first half of 2020. With 1.8 times logic density and 15% speed gain and an ARM A72 core compared with 7-nanometer, we believe our N5 technology is the most competitive in the industry. With the best density performance, power and the best transistor technology, we expect most of our customers who are using 7-nanometer today will adopt 5-nanometer. With N5, we are expanding our customer product portfolio and increasing our addressable market. Thus, we are confident that 5-nanometer will also be a large and long-lasting node for TSMC.

To be clear TSMC 5nm chips will be in Apple products next year. I have read reports that TSMC released 6nm because 5nm was late which is fake news. I know many companies that are taping-out at 5nm and it is on track and meeting expectations. More details will be available on SemiWiki after the symposium so stay tuned.

  • Now I’ll talk about the ramp up of N7 and N7+ and introduction of N6. We are seeing strong tape-out activity at N7, which include HPC, IoT and automotive. Meanwhile, our N7+, which adopts EUV for few critical areas, has already started volume production now. The yield rate is comparable to N7. We’ll reaffirm N7 and N7+ will contribute more than 25% of our wafer revenue in year 2019.

If you look at TSMC’s Q4 2018 revenue split, 50% is FinFET processes and 50% is mature CMOS nodes. In Q4 2017 FinFET processes were 45% and in Q4 2016 it was 33%. In Q1 2019 FinFET revenue dropped to 42%, not a good sign, let’s blame cryptocurrency.

  • As we continue to improve our 7-nanometer technology and by leveraging the EUV landing form, N7+, we now introduce N6 process. N6 has three major advantage. First, N6 have 100% compatible design rules with N7, which allows customer to directly migrate from N7-based design, which substantially shorten the time-to-market. Second, N6 can deliver 18% higher logical density as compared to N7 and provide customer with a highly competitive performance-to-cost advantage. Third, N6 will offer shortened cycle time and better defect density. Risk production of N6 is scheduled to begin in first quarter year 2020 with volume production starting before the end of 2020.

N6 is a little bit confusing thus far. Hopefully we can get it cleared up at the TSMC Symposium. From what I understand N7 and N7+ are not design rule compatible since N7+ has EUV. N6 is N7+ with an additional layer of EUV which helps with density. Saying N6 and N7+ are design rule compatible makes sense but is N6 really design rule compatible with N7?

  • Finally, I will talk about the HPC as our most important growth driver in the next five years. CPU, AI accelerator and networking will be the main growth area for our HPC platform. With the successful ramp of N7, N7+ and the upcoming N6 and N5, we are able to expand our customer product portfolio and increase our addressable market to support applications, such as data center, PC and tablets. Meanwhile, we also see networking querying thanks to 5G infrastructure deployment over the next few years. We are truly excited about our growth opportunities in HPC. Thank you for your attention.

AI is a trending term on SemiWiki and readership is all over the map. I seriously doubt it will be a quick bubble like cryptocurrency or even a 10 year bubble like mobile. In my opinion AI will be with us for a very long time and it will consume leading edge wafers like a zombie apocalypse, absolutely.

From what I have heard EUV throughput is still ramping up so my fingers are crossed for 5nm. Hopefully EUV is covered in more detail next week at the TSMC Symposium. I will also get a refresh from our resident EUV expert Scott Jones. In fact, he has just posted an EUV blog from SPIE:

SPIE Advanced Lithography Conference – Imec and Veeco on EUV

Bottom line: The second half of 2019 will be good for TSMC and 2020 will be even better. My prediction today for TSMC in 2020 is back to double digit growth. Remember, now that Intel is out of 5G modems TSMC will get the modem business back from Apple next year via the 7nm QCOM modem plus other 5G modem business. 2020 will be the beginning of a beautiful 5G friendship.

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Samsung 5nm and TSMC 6nm Update

Samsung 5nm and TSMC 6nm Update
by Daniel Nenni on 04-16-2019 at 12:00 pm
Categories: FinFET, Foundries, Samsung Foundry, TSMC
5 Comments

TSMC and Samsung continue to raise the competitive bar for FinFET foundry market share with dueling announcements this week. As I mentioned previously in the blog Semiconductor Foundry Landscape Update 2019, FinFETs are the market to watch with the coming onslaught of 5G and AI chips on the edge, in the cloud, and in our autonomous cars.

Yesterday Samsung announced that 5nm EUV is ready to go with PDKs, EDA Tools, IP, and MPWs. Samsung already has 14nm, 11nm, 10nm, 8nm, 7nm EUV, and 6nm EUV production ready. Samsung’s 5nm FinFET process technology provides up to a 25% increase in logic area efficiency with 20% lower power consumption or 10% higher performance over their 7nm process.

“In successful completion of our 5nm development, we’ve proven our capabilities in EUV-based nodes,” said Charlie Bae, Executive Vice President of Foundry Business at Samsung Electronics. “In response to customers’ surging demand for advanced process technologies to differentiate their next-generation products, we continue our commitment to accelerating the volume production of EUV-based technologies.”

Samsung foundry’s EUV-based process technologies are currently being manufactured at the S3-line in Hwaseong, Korea. Additionally, Samsung will expand its EUV capacity to a new EUV line in Hwaseong, which is expected to be completed within the second half of 2019 and will start production ramp-up for next year.

Mr. Bae continued, “Considering the various benefits including PPA and IP, Samsung’s EUV-based advanced nodes are expected to be in high demand for new and innovative applications such as 5G, artificial intelligence (AI), high performance computing (HPC), and automotive. Leveraging our robust technology competitiveness including our leadership in EUV lithography, Samsung will continue to deliver the most advanced technologies and solutions to customers.”

Not to be outdone, TSMC today announced 6nm EUV which fills out their FinFET offering of 16nm, 12nm, 10nm, 7nm, 7nm EUV, 6nm EUV, and 5nm EUV. TSMC 6nm offers an 18% density advantage over 7nm.

TSMC announced 5nm ecosystem completion last week which offers a 1.8X logic density and 15% speed gain versus 7nm. TSMC’s 6nm process delivers 18% higher logic density over the 7nm process. At the same time, its design rules are fully compatible with TSMC’s proven 7nm technology.

“TSMC N6 technology will further extend our leadership in delivering product benefits with higher performance and cost advantage beyond the current N7,” said Dr. Kevin Zhang, TSMC Vice President of Business Development. “Building upon the broad success of our 7nm technology, we’re confident that our customers will be able to quickly extract even higher product value from the new offering by leveraging a well-established design eco-system today.”

This is great news, we now have a legitimate two horse race for our FinFET design starts. The question is where is all of the IP going to come from for these new nodes? There are thousands of silicon proven FinFET based IPs in the ecosystem that will need to be tuned and verified to each and every node. It certainly is a good time to be a Semiconductor IP or IP management software company, absolutely.

About TSMC
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The company supports a thriving ecosystem of global customers and partners with the industry’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. TSMC serves its customers with annual capacity of about 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States, and China, and provides the broadest range of technologies from 0.5 micron plus all the way to foundry’s most advanced processes, which is 7-nanometer today. TSMC is the first foundry to provide 7-nanometer production capabilities, and is headquartered in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.

About Samsung Electronics Co., Ltd.
Samsung inspires the world and shapes the future with transformative ideas and technologies. The company is redefining the worlds of TVs, smartphones, wearable devices, tablets, digital appliances, network systems, and memory, system LSI and foundry. For the latest news, please visit the Samsung Newsroom at http://news.samsung.com.

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A Collaborative Driven Solution

A Collaborative Driven Solution
by Alex Tan on 04-11-2019 at 7:00 am
Categories: EDA, FinFET, Foundries, Siemens EDA, TSMC

Last week TSMC announced the availability of its complete 5nm design infrastructure that enables SoC designers to implement advanced mobile and high-performance computing applications for the emerging 5G and AI driven markets. This fifth generation 3D FinFET design infrastructure includes technology files, PDKs (Process Design Kits), tools, flows and IPs –all of which have been developed and validated by multiples silicon test vehicles through earlier collaboration with leading EDA and IP vendors.

Normally each process node shift is expected to deliver significant improvements in one or more of PPAC (Performance, Power, Area or Cost) design metrics. For example, the innovative scaling features in full-fledged EUV 5nm node provides a 1.8X logic density and 15% speed gain based on the ARM® Cortex®-A72 core testcase. While the process refresh update seems so regular (about every 18 to 24 months), the intricacies imposed by the new process technology keep rising and its direct impacts on the EDA space have been constantly endured foremost by both the physical verification and circuit simulation tools.

Mentor, a Siemens Business has been the industry leader in providing physical verification solution through its Calibre physical verification (PV) platform, which includes Calibre nmDRCand Calibre nmLVS. As a design signoff tool, there are three most sought criteria in PV: accuracy, reliability and performance –all of which are attainable through tight collaboration with both the targeted foundry and alpha customers. Foundry rigorous trials such as TSMC applied double-blind QA procedure has helped to facilitate tool and design flow readiness.

Design Density, Performance and Rule Complexity
As physical verification has evolved around design rules development and its verification, the rule complexity is directly proportional to the device and interconnect technology of the underlying process. Despite the slow down of Moore’s law, design density is still increasing driven by the relentless compute power demand to process data on the cloud and edge. Historically, transistor count has been used as the classic metric to measure the forward trend. Recent multi-core design and increased IPs inclusion trends have driven the transistor counts, pushing the number of design rules and the associated operations needed to implement those rules upward. The non-linear growth of DRC rules prompts challenges to a timely adoption of new process shift by the design teams.

Deep Collaboration and EDA Tool Certifications
A key success criterion for tool certification is to incorporate new functionality based on the foundry requirements in the early stages of process node development. During this development stage, foundry needs to step through the learning curve and bootstrap their prior known node experiences to enhance the overall ramp time. Over the years, Mentor has participated in repeat successful collaboration including three main physical verification areas (DRC, LVS, xACT/xRC) with multiple foundries.

To have foundries utilize Calibre tools internally as they develop a new process provides the most valuable return as it allows earlier identification and simultaneous fine-tuning of foundry design requirements and hardening the verification tools with any needed rules. For example, Mentor Calibre has been part of the TSMC EDA tool certification.

“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,”said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

In very advanced node such as TSMC 5nm, a deeper design-technology co-optimization is also necessary. Such earlier and heuristic collaborative efforts among foundry, EDA provider and the alpha customer will culminate in a number of pilot tapeouts and the start of silicon risk production cycle. For example, the flurry of pilot 5nm tapeouts occurring in the last few quarters will be followed by silicon bring-up in the second half of 2019.

Tool Capacity, Memory and Runtime
Tool scalability involves several variables such as code vectorization and optimal memory footprint. Memory usage is a key metric that also ties to tool performance. The diagram in figure 2 shows the normalized Calibre engine performance trend as a result of incorporating continuous speed improvements over several process nodes. In two recent Calibre nmDRC versions across six different 7 nm designs, Mentor reported a consistent 40-50% decrease in memory usage as the underlying data structures and memory management techniques were improved.

Calibre facilitates pre- and post- physical validations by providing ease-of-use interfaces for navigating and visualizing complex verification errors. Without proper integration and planning, completing a verification task may incur significant post-run analysis time. This can be minimized by enabling the many available Calibre features to configure, launch, review, and debug within the designer’s chosen flow as it is built to accommodate many third party and design team internal flows. For example, Calibre has uniquely used special debug layers for double-patterning debugging, and automated waiver processing for masking out IP errors during chip integration debugging.


The immense challenges of a process node shift have strained silicon ecosystem stakeholders which include foundries, designers and EDA companies. Aside from having ample solution expertise and commitment, EDA company such as Mentor has resorted in deep collaboration and partnership with foundries and designers to perform early process exploration and enabling successful deployment of the needed toolset including Calibre physical verification tools.

Check HERE for more discussion on Mentor Calibre physical verification tool for advanced process node.

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Semiconductor Foundry Landscape Update 2019

Semiconductor Foundry Landscape Update 2019
by Daniel Nenni on 03-29-2019 at 5:00 am
Categories: FD-SOI, FinFET, Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, TSMC

The semiconductor foundry landscape changed in 2018 when GLOBALFOUNDRIES and Intel paused their leading edge foundry efforts. Intel quietly told partners they would no longer pursue the foundry business and GF publicly shut down their 7nm process development and pivoted towards existing process nodes while trimming headcount and repositioning assets.

Moving forward this puts TSMC in a much more decisive position in the foundry landscape which has been talked about by the mainstream media. The interesting thing to note is that the semiconductor foundry business was based on the ability to multisource a single design amongst two, three or even four different foundries to get better pricing and delivery. That all changed of course with 28nm which went into production in 2010.

TSMC chose a different 28nm approach than Samsung, GLOBALFOUNDRIES, UMC and SMIC which made the processes incompatible. Fortunately for TSMC their 28nm HKM gate-last approach was the only one to yield properly which gave them a massive lead that had not been seen before. While Samsung and GF struggled along with gate-first HKM, UMC and SMIC changed their 28nm to the TSMC gate-last implementation and captured 2nd source business from TSMC following the long time foundry tradition.

Again it changed back to single source when FinFET technology came to TSMC in 2015. FinFET is a complicated technology that cannot be cloned without a licensing agreement. TSMC started with 16nm followed by 12nm, 10nm, 7nm (EUV), and 5nm (EUV) which will arrive in 2020. Samsung licensed their 14nm to GF which is the only second sourced FinFET process. Samsung followed 14nm with 10nm, 8nm, 7nm (EUV), 5nm (EUV) will follow.

Today there are only two leading edge foundries left, TSMC and Samsung. TSMC is currently the foundry market leader and I see that increasing when mature CMOS process nodes that have second, third, and even fourth sources become obsolete and the unclonable FinFET processes take over the mature nodes.

If you look at TSMC’s revenue split, today 50% is FinFET processes and 50% is mature CMOS nodes (Q4 2018). In Q4 2017 FinFET processes were 45% and in Q4 2016 it was 33%. As the FinFET processes grow so does TSM’s market share and that will continue for many years to come. As it stands today TSMC has revenues of $33.49B in 2018 which represents a 48% foundry market share. Revenue growth in 2019 may be limited due to the global downturn but TSMC should continue to claim market share due to their FinFET dominance.

In 2018 GLOBALFOUNDRIES, the #2 foundry, pivoted away from leading edge process development (7nm/5nm) to focus on mature processes (14nm, 28nm, 40nm, 65nm, 130nm and 180nm) and the developing FD-SOI market with 22FDX and 12FDX following that.

In 2018 UMC, the #3 foundry, still struggled with 14nm which forced long time ASIC partner Faraday to sign an agreement with Samsung Foundry for advanced FinFET processes. Today, UMC relies on mature process nodes: 28nm, 40nm, 55nm, 65nm, and 90nm for the bulk of their revenue from a select base of high volume customers. Even when UMC perfects FinFETs at 14nm it will not be TSMC compatible so the market will be limited. UMC’s 2018 revenue of $4.91B represents a 7.2% market share being the second largest publicly traded foundry (GF is private).

Samsung, the #4 foundry, is in production at 45nm, 28nm, 28FDSOI, 18FDSOI, 14nm, 11nm, 10nm, 8nm, and 7nm. Samsung is a fierce competitor and gained significant customer traction at 14nm splitting the Apple iPhone business with TSMC. Even today Samsung is a close second to TSMC in 14nm if you include GF 14nm which was licensed from Samsung. Samsung was also the first to “full” EUV at 7nm. Samsung’s largest foundry customer of course is Samsung itself being the #1 consumer electronics company. Qualcomm is also a very large Samsung Foundry customer amongst other top fabless semiconductor companies including IBM and AMD. The foundry business was always about choices for wafer manufacturing so you can bet Samsung will get their fair FinFET market share moving forward, absolutely.

In 2018 SMIC, the #5 foundry, also struggled with FinFETs. Mass 14nm production is slated to begin in 2019, again it is not TSMC compatible but in China it does not necessarily have to be. Today SMIC is manufacturing 90nm and 28nm wafers mostly for fabless companies in China. When 14nm hits high volume manufacturing the China FinFET market will likely turn to SMIC in favor of non Chinese 14nm fabs as it did at 90nm and 28nm. The challenge SMIC has always faced is yield and capacity and that will continue. In 2018 SMIC recorded sales of $785M which represents a 4.5% foundry market share with the majority of it based in China.

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TSMC and Semiconductors 2019 and Beyond

TSMC and Semiconductors 2019 and Beyond
by Daniel Nenni on 01-22-2019 at 7:00 am
Categories: Foundries, TSMC
10 Comments

TSMC has always been my bellwether and for 2019 I think we need to pay careful attention. Bad economic news has been spreading inside the fabless semiconductor ecosystem (tool and IP budgets have been tightening) but I think it is a bit premature. Let’s take a look at the TSMC 2018 Q4 earnings call and talk more about it in the comments section:

  • Q1 of $7.3B to $7.4B, down 14%
  • TSMC expects 2019 revenue to grow 1% to 3% compared to 6.5% in 2018
  • TSMC cites inventory congestion
  • TSMC expects weak demand until 2H19
  • TSMC 2018 CAPEX 10.5B ($10-11B 2019)
  • Predicts global GDP growth from 3.2% in 2018 to $2.6% in 2019
  • Predicts 2019 non memory semiconductor growth at 1%
  • Predicts long term TSMC growth of 5%-10% CAGR

Revenue by technology Q4 2018:

  • 7-nanometer 23%
  • 10-nanometer 6%
  • 16/20-nanometer 21%.
  • 28-nanometer and below 67%

Full year revenue by technology 2018:

  • 7-nanometer 9% (25% in 2019)
  • 10-nanometer 11%
  • 16/20-nanometer 23%
  • 28-nanometer and below 63%

Contribution by application in 2018

  • Communications 56% (+1%)
  • Industrial/Standard 23% (+3%)
  • Computer 14% (+61%)
  • Consumer 7% (-17%)

(Smartphones 45%, HPC 32%, IoT 6%, Automotive 5%. 5G and AI will kick in this year and next).

Comments from CC Wei:
Our N5 technology development is well on track, with customer tape-out schedule for first half 2019 and volume production ramp in first half 2020. We are already in preparation for N5’s ramp. All applications that are using 7-nanometer today will adopt 5-nanometer. In addition, we are expecting the customer product portfolio at N5 and see expanding addressable market opportunities. We expect more applications in HPC to adopt N5. Thus we are confident that N5 will also be a large and long-lasting node for TSMC.

TSMC all but locked up 7nm and making the transition from 7N to 5N should pave the way for another big node for TSMC. Samsung however will be better prepared to compete with TSMC at 5nm so there may be a bigger split. For example, AMD is a big upside for TSMC 7nm in 2H 2019 but from what I am told AMD will split manufacturing between TSMC and Samung at 5nm. The same thing with Qualcomm and others. As I have mentioned before, multi-sourcing has always been the foundation of the fabless semiconductor ecosystem and at the leading edge it is TSMC and Samsung.

Now let’s take a look at the Analyst Q&A:

The first question was on CAPEX. TSMC had previously said CAPEX of $10-12B would be sufficient for 5-10% growth. In 2018 TSMC CAPEX was $10.5B and in 2019 CAPEX is expected to be $10-11B. TSMC is a master of fab and equipment re-use so I do not see a CAPEX problem here as others have. For example N7+ will be a very quick node so the fab space and EUV machines will be reallocated to 5nm in short order.

The next question was on revenue by application which I found interesting. From what I have seen on SemiWiki, automotive is more of a bubble than a major growth area. IoT of course is booming. AI I guess is part of HPC but is overshadowed by the cryptocurrency bubble burst so you hardly notice it.

Roland Shu
Thank you. Happy New Year. First question is, C.C., you said for the mobile business this year, you still expect some growth, but under your overall year, on the whole year revenue growth just slightly. So how about the growth of the other platform products, IoT, HPC and automotive?

C.C. Wei
Okay, Roland, you asked a good question. Smartphone grows slightly. IoT grows double-digit. Automotive will be flat. HPC, if we’re excluding the cryptocurrency mining, HPC also grows slightly. But cryptocurrency is a big drop from 2018 to 2019. So if we put the cryptocurrency together in the HPC, it’s a big drop. It’s almost a double-digit.

The rest of the questions were about trying to figure out why the slowdown happened and what TSMC sees for the future. In my experience, at the beginning of a slowdown such as this, smart CEOs bite the bullet and give very conservative forecasts moving forward so they only have to deliver bad news once a year. This is what TSMC is doing in my opinion, being very conservative.

In my opinion smartphone sales have been sluggish due to market saturation, price gouging, and lack of innovation and will continue to be sluggish until we see 5G phones. Everyone will want 5G and very soon everyone will need 5G to keep up with the new features the extra bandwidth will bring. 5G really is a known term amongst the masses. I heard kids calling parents 3G as an insult when 4G came out.

Price is a big issue for me. We used to get big breaks on new phones from carriers with 2 year contracts. Now we don’t so we hold on to them longer. The carriers now offer low monthly payments on new phones in lieu of discounts but you still have to pay taxes on the retail price. It is a better deal but not by much and a big departure from when we got free phones for a new contract.

Bottom line:I don’t think this year will be as bad for the semiconductor industry as some are predicting. We absolutely got ahead of ourselves with the last two double digit growth years and 1H 2019 will be the correction. But moving forward I too see great promise in 5G and AI for companies making chips, absolutely.

You can see the whole transcript HERE.