TSMC recently held their annual Technology Symposium in Santa Clara, CA. The presentations provide a comprehensive overview of their technology status and upcoming roadmap, covering all facets of the process technology and advanced packaging development. This article will summarize the highlights of the advanced packaging… Read More
TSMC 2022 Technology Symposium Review – Process Technology Development
TSMC recently held their annual Technology Symposium in Santa Clara, CA. The presentations provided a comprehensive overview of their status and upcoming roadmap, covering all facets of process technology and advanced packaging development. This article will summarize the highlights of the process technology updates… Read More
Three Key Takeaways from the 2022 TSMC Technical Symposium!
The TSMC Technical Symposium is today so I wanted to give you a brief summary of what was presented. Tom Dillinger will do a more technical review as he has done in the past. I don’t want to steal his thunder but here is what I think are the key takeaways. First a brief history lesson.
The history of TSMC Technology Development with 12 key… Read More
Intel 4 Deep Dive
As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12).
“Intel 4 CMOS Technology Featuring Advanced FinFET Transistors… Read More
An Update on In-Line Wafer Inspection Technology
From initial process technology development (TD) to high volume manufacturing (HVM) status for a new node, one of the key support functions to improve and maintain yield is the in-line wafer inspection technology. Actually, there are multiple inspection technologies commonly employed, with tradeoffs in pixel resolution,… Read More
Inverse Lithography Technology – A Status Update from TSMC
“Inverse lithography technology (ILT) represents the most significant EDA advance in the last two decades.” Danping Peng from TSMC made that assertion at the recent SPIE Advanced Lithography + Patterning Conference, in his talk entitled: ILT for HVM: History, Present, and Future. This article summarizes the highlights… Read More
0.55 High-NA Lithography Update
At the recent SPIE Advanced Lithography + Patterning Conference, Mark Phillips from Intel gave an insightful update on the status of the introduction of the 0.55 high numerical aperture extreme ultraviolet lithography technology. Mark went so far as to assert that the development progress toward high-NA EUV would support … Read More
TSMC N3 will be a Record Setting Node!
With the TSMC Technical Symposium coming next month there is quite a bit of excitement inside the fabless semiconductor ecosystem. Not only will TSMC give an update on N3, we should also hear details of the upcoming N2 process.
Hopefully TSMC will again share the number of tape-outs confirmed for their latest process node. Given… Read More
Intel and the EUV Shortage
In my “The EUV Divide and Intel Foundry Services” article available here, I discussed the looming EUV shortage. Two days ago, Intel announced their first EUV tool installed at their new Fab 34 in Ireland is a tool they moved from Oregon. This is another indication of the scarcity of EUV tools.
I have been tracking EUV system production… Read More
Can Intel Catch TSMC in 2025?
At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation.
ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the clear leader. Following that conference,… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet