At IEDM Intel and Micron presented “A Floating Gate Based 3D NAND Technology With CMOS Under Array” authored by Krishna Parat and Chuck Dennison.
As I previously discussed in my blog on the IEDM memory short course and blog on IMEC’s work on high mobility 3D NAND channels, continuing to scale 2D Flash has become extremely difficult and the major Flash producers are all moving to 3D NAND.
The memory short course blog can be accessed here.
The IMEC high mobility channel for 3D NAND can be accessed here.
Samsung was the first to introduce 3D NAND with their Terabit Cell Array Transistor (TCAT) and Toshiba has been in hot pursuit with their Bit Cost Scalable (BiCS) approach. Both of these approaches plus proposed 3D NAND from SK Hynix and Macronix have all been based on a charge trap devices where a silicon nitride layer is used to trap electrons.
The basic process for these devices can be thought of in three parts:
- CMOS – the fabrication of CMOS to control access to the memory array.
- Memory array – deposition of the memory layers, channel, slot and stair step formation.
- Interconnect – interconnect of the CMOS and memory array.
To-date the 3D NAND devices in production have been charge trap based memory cells and the CMOS has been arranged off to the sides of the memory array.
In the Intel-Micron paper the first floating gate 3D NAND cell is described as well as the first instance of the CMOS being fabricated under the memory array.
The fabrication of CMOS under the memory array follows a flow similar to CMOS off to the side but adds interconnect that will also be under the memory array. We expect a pair of tungsten interconnect layers will be required.
The memory array fabrication begins with deposition of oxide and polysilicon layers pairs. The devices described in the paper has 32 memory layers plus select transistor layers and dummy layers. After the layers are deposited the array formation proceeds as follows:
[LIST=1]
Although not specifically addressed I would expect this to be followed by slit and stair step processes.
I have heard a rumor that Intel-Micron creates their stair step with far fewer masks than Samsung. The challenge of stair step formation is a that a thick photoresist layer is deposited, one film pair is etched and then the photoresist image is “shrunk” and another film pair is etched. Because the photoresist film is getting thinner with each “shrink” there is a limit to how many layer pairs can be done by each mask. I have heard Intel-Micron gets more film pairs out of each mask, possibly by etching stairs that are narrower.
Following the memory array formation, interconnect would be fabricated similar to the Samsung and Toshiba processes with the additional need to etch vias down to the CMOS under the memory array.
The Intel-Micron process trades added process complexity to put the CMOS under the memory array against die area, so how do they do?
Samsung initially entered the market with a 24 layer 2 bit/cell device; they then introduced 32 layer 2 bit per cell and 3 bit per cell devices, and recently announced a 48 layer 3 bit per cell device. So how does the Intel-Micron 32 layer 2 bit per cell and 3 bit per cell devices compare? The following table summarizes the five parts. Please note that a die size for the Samsung 48 layer devices is not yet available and the value presented is our estimate.
[TABLE] align=”center” border=”1″
|-
| style=”width: 106px; text-align: center” | Company
| style=”width: 69px; text-align: center” | 3D layers
| style=”width: 66px; text-align: center” | Bits/cell
| style=”width: 108px; text-align: center” | Capacity (Gb)
| style=”width: 96px; text-align: center” | Die size (mm2)
| style=”width: 114px; text-align: center” | Density (Gb/mm2)
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 24
| style=”width: 66px; text-align: center” | 2
| style=”width: 108px; text-align: center” | 128
| style=”width: 96px; text-align: center” | 132.2
| style=”width: 114px; text-align: center” | 0.97
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 2
| style=”width: 108px; text-align: center” | 88
| style=”width: 96px; text-align: center” | 87.3
| style=”width: 114px; text-align: center” | 0.98
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 3
| style=”width: 108px; text-align: center” | 128
| style=”width: 96px; text-align: center” | 68.9
| style=”width: 114px; text-align: center” | 1.86
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 48
| style=”width: 66px; text-align: center” | 3
| style=”width: 108px; text-align: center” | 256
| style=”width: 96px; text-align: center” | 91.9 (est)
| style=”width: 114px; text-align: center” | 2.49
|-
| style=”width: 106px; text-align: center” | Intel-Micron
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 2
| style=”width: 108px; text-align: center” | 256
| style=”width: 96px; text-align: center” | 168.5
| style=”width: 114px; text-align: center” | 1.52
|-
| style=”width: 106px; text-align: center” | Intel-Micron
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 3
| style=”width: 108px; text-align: center” | 384
| style=”width: 96px; text-align: center” | 168.5
| style=”width: 114px; text-align: center” | 2.28
|-
From the table it can be seen that the new 32 layer Intel-Micron device with the CMOS under the memory array is significantly denser than the Samsung 32 layer device. Of course as Intel-Micron are introducing their 32 layer device Samsung is introducing a 48 layer device and undoubtedly hard at work on putting the CMOS under the memory array on their devices as well.
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