At IEDM IMEC presented “MOCVD In[SUB]1-x[/SUB]Ga[SUB]x[/SUB]As high mobility channel for 3-D NAND Memory” authored by E. Capogreco, J. G. Lisoni, A. Arreghini, A. Subirats, B. Kunert, W. Guo, T. Maurice, C.-L. Tan, R. Degraeve, K. De Meyer, G. Van den bosch, and J. Van Houdt.
On December 15[SUP]th[/SUP] I had the opportunity to have a conference call with Arnaud Furnemont, director of memory department, at IMEC and discuss this work.
With the well published difficulties with continuing to scale 2D NAND, all of the leading NAND Flash producers have introduced 3D NAND. Micron has even gone as far as to announce that 16nm will be their last 2D NAND generation.
For 3D NAND a stack of alternating layers is deposited, either oxide-nitride or oxide-poly and then a channel opening is etched down through the stack. Currently 32 layer devices are in production with 48 layer devices being introduced. The long term plan for 3D NAND is to continue to add layers to the stack until over a hundred layers will be in use creating 1 terabit memories. There is also the need to create slits down through the stack and a stair-step at the array edge for interconnect.
Some of the key integration challenges for 3D NAND are:
- Stress in the memory stack.
- Creating holes and slits through such a tall stack.
- Resistance of the channel.
The work in this paper is specifically targeted at channel resistance.
In 2D NAND the memory cell channels are single crystal silicon with relatively good mobility.
For 3D NAND, once the channel opening is etched down through the memory stack, a polysilicon tube referred to as a “macaroni channel” is formed in the etch opening. As the number of memory stack layers increases, the height of the macaroni channel increases. Because polysilicon has lower mobility that single crystal silicon, the channel resistance becomes a problem as the channel height increases.
In this work a three memory layer stack was created using the Bit-Cost Scalable (BiCS) approach championed by Toshiba and San Disk (oxide-poly layers). 45nm channel openings were etched down through the layers and an InGaAs channel was then grown. The resulting channels showed a 10x improvement versus their process of record polysilicon channel.
To-date the work is based on the BiCS process. I asked about the TCAT process Samsung utilizes particularly in light of Samsung being the first to market with 3D NAND. Arnaud said that TCAT will be next. Also, the work presented at IEDM just covered the channel mobility, since the original work was completed they have demonstrated program/erase of data and saw no change in the memory cells versus the POR.
For a full implementation of this process there is still work to do:
- They need to integrate a metal gate. When the memory cell is based on a nitride trap layers such as BiCS and TCAT use a metal gate is needed to create a high work function. The Micron floating gate 3D NAND I will address in a separate blog wouldn’t need a metal gate.
- Currently the channel is solid and they need to create a macaroni channel.
This work is an important step in addressing the challenges of continuing to scale 3D NAND.