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TSMC Responds to Intel’s 14nm Density Claim!

TSMC Responds to Intel’s 14nm Density Claim!
by Daniel Nenni on 01-21-2014 at 9:30 pm

TSMC responded to Intel’s 14nm density advantage claim in the most recent conference call. It is something I have been following closely and have written about extensively both publicly and privately. Please remember that the fabless semiconductor ecosystem is all about crowd sourcing and it is very hard to fool a crowd of semiconductor professionals, absolutely. To see Intel’s infamous density presentation click HERE.

First let’s take a look at what TSMC had to say:

Morris Chang – Chairman:So I now would ask Mark Liu to speak to TSMC’s competitiveness versus Intel and Samsung:

Let me comment on Intel’s recent graph shown in their investor meetings, showing on the screen. I — we usually do not comment on other companies’ technology, but this — because this has been talking about TSMC technology and, as Chairman said, has been misleading, to me, it’s erroneous based on outdated data. So I’d like to make the following rebuttal:

On this new graph, the vertical axis is the chip area on a large scale. Basically, this is compared to chip area reduction. On the horizontal axis, it shows the 4 different technologies: 32, 28; 22, 20; 14, 16-FinFET; and 10-nanometer. 32 is Intel technology, and 28 is TSMC technology so is the following 3 nodes, the smaller number, 20, around — 14-FinFET is Intel, 16-FinFET is TSMC. On the view graph shown at Intel investor meeting, it is with the gray plot, showing here. The gray plot showed the 32- and the 20-nanometer TSMC is ahead of the area scaling and — but — however, with 16, the data — gray data shows a little bit uptick. And following the same slope, go down to the 10-nanometer, was the correct data we show on the red line. That’s our current TSMC data. The 16, we have in volume production on 20-nanometer. As C.C. just mentioned, this is the highest density technology in production today.

We take the approach of significantly using the FinFET transistor to improve the transistor performance on top of the similar back-end technology of our 20-nanometer. Therefore, we leverage the volume experience in the volume production this year to be able to immediately go down to the 16 volume production next year, within 1 year, and this transistor performance and innovative layout methodology can improve the chip size by about 15%. This is because the driving of the transistor is much stronger so that you don’t need such a big area to deliver the same driving circuitry.

And for the 10-nanometer, we haven’t announced it, but we did communicate with many of our customers that, that will be the aggressive scaling of technology we’re doing. And so in the summary, our 10 FinFET technology will be qualified by the end of 2015. 10 FinFET transistor will be our third-generation FinFET transistor. This technology will come with industry’s leading performance and density. So I want to leave this slot by 16-FinFET scaling is much better than Intel’s set but still a little bit behind. However, the real competition is between our customers’ product and Intel’s product or Samsung’s product.

Morris Chang – Chairman:Thank you, Mark. In summary, I want to say the following: First, in 2014, we expect double-digit revenue growth and we expect to maintain or slightly improve our structural profitability. As a result, we expect our profit growth to be close to our revenue growth. In 2014, the market segment that most strongly fuels our growth is the smartphone and tablet, mobile segment. The technologies that fuel our growth are the 20-SoC and the 28 high-K metal gate, in both of which we have strong market share. In 2015, our strong technology growth will be 16-FinFET. We believe our Grand Alliance will outcompete both Intel and Samsung, outcompete.

If there is anyone out there that doubts these numbers please post in the comment section or send me a private email. I will follow up with a rebuttal blog based on feedback next week.

More Articles by Daniel Nenni…..

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