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A Power Optimization Flow at the RTL Design Stage

A Power Optimization Flow at the RTL Design Stage
by Daniel Payne on 01-21-2014 at 10:20 pm

SoC designers can code RTL, run logic synthesis, perform place and route, extract the interconnect, then simulate to measure power values. Though this approach is very accurate, it’s also very late in the implementation flow to start thinking about how to actually optimize a design for the lowest power while meeting all of the other design requirements. Ideally, you would want a flow that starts with your RTL code at the design phase and then provides a method to estimate power and even provide feedback on how to best reduce power long before physical implementation even begins.

Here is a flow-chart for such a methodology where power estimation happens early during the design phase, instead of too late:

The first box depicts how at the architectural stage a decision is made about using voltage domains, power domains, and clock gating techniques. Any IP re-used from a previous design can be quickly tallied in this new design for an early power estimate.

At the second box you should have enough RTL together so that power numbers can be added up based on re-use or spreadsheet estimates. There’s even commercial EDA software from Atrentacalled SpyGlass Power that can quickly estimate power numbers at the RTL design phase. Either the manual or automated approach will benefit your project early in the process to see if the power requirements have been met.

Most designs will not be within the power budget at this early design stage, so it’s time to move on to the third step: Power Reduction methods. The SpyGlass Power tool will help automate this power reduction process by changing an RTL design:

  • Applies gate enables, then provides an activity-based power calculation
  • Inserts clock-gates
  • Checks existing clock enable
  • Identifies new clock enables

You are likely also adding level shifters between voltage domains and inserting isolation logic. These changes and SpyGlass Power changes need to be verified against the original design intent, which is the fourth step in the flow-chart.

Implementation is the fifth step and it’s where logic synthesis transforms RTL into technology-specific cells for use by a place and route tool, driven by timing, DFT and placement constraints.

Once the IC layout is complete a final post-layout power verification is required to ensure that no surprises or errors have crept in.

Power Saving Overview

SoC power can be divided into dynamic and static categories. Examples of controlling dynamic power are:

  • Using voltage domains
  • Adding clock gating techniques

And examples for managing static power include:

  • Multiple power domains where an entire domain can be put to sleep
  • Using multi-voltage threshold transistors

Power Estimation in SpyGlass Power

This tool can calculate power by cycle, average for leakage, internal and switching, then display it graphically or numerically:

Power Reduction

Pawan Fangaria blogged recently about many of the clock gating techniques used for power reduction in more detail. Taking automation one step further SpyGlass Power has a feature called AutoFix that finds new clock enable opportunities then goes ahead and fixes the RTL code to take advantage of it.

To put your mind at ease about the integrity of any changes to RTL you can run a sequential equivalency checking (SEC) tool on the original RTL versus AutoFixed version.

Summary

Estimating and reducing power are popular topics for SoC designers today, fortunately we have EDA tools in place by vendors like Atrenta that help automate the task in a timely fashion by letting you work with early RTL to see if your power requirements are being met.

Further Reading

A 12 page white paper from Guillaume Boillet and Kiran Vittal is available at Atrenta, and you’ll need to complete a simple registration process before downloading.

lang: en_US

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