Webinar – IP Design Considerations for Real-Time Edge AI SystemsIt is well-known that semiconductor growth is driven…Read More
WEBINAR: Design and Stability Analysis of GaN Power Amplifiers using Advanced Simulation ToolsWhy should high frequency circuit designers consider stability…Read More![[white paper] Parasitic Analysis Figures](https://semiwiki.com/wp-content/uploads/2025/10/Fig1-net-level-visualization.jpg)
Visualizing hidden parasitic effects in advanced IC design By Omar Elabd As semiconductor designs move below…Read More
Statically Verifying RTL Connectivity with SynopsysMany years ago, not long after we first…Read More
Assertion IP (AIP) for Improved Design VerificationOver the years design reuse methodology created a…Read More
You are going to DAC. And you don’t want to eat a Moscone Center rubber chicken Caesar salad for lunch. But you lack local knowledge. So here are some places within a 10 minute walk. These are just places I like. Nobody is paying me to recommend them.
Places to eat
The food court in the San Francisco Center on Market Street between… Read More
What’s new with Glofo? Quite a bit actually. It was interesting to see a Made in America: Global Companies Expand in U.S. Towns segment on semiconductors! Give it a look, I enjoyed it. It’s an election year, jobs are key to any election, so it did not surprise me to see President Obama making the rounds:… Read More
In one of Portlandia’s TV program sketches, there is a funny interchange between a carrier salesperson and Fred Armisen (of SNL fame) who was trying to buy a phone. One chuckle line was a statement by the seller that the phone was free after paying for it and that there was a one-time annual fee. With this anecdote as a mental backdrop,… Read More
We are all aware that at 28nm and below several types of complex layout effects manifest themselves into the design and pose a herculean task, with several re-spins to correct them at pre-tapeout. It’s apparent that the layout needs to be correct by construction at the very beginning during the design stage.
Collaboration between EDA, Foundry and Design was the key idea today in a webinar hosted by IBM and Cadence about 20nm custom IC design. The three presenters were:
John Stabenow, Cadence
Jeremiah Cessna, Cadence
Keith Barkley, IBM… Read More
There’s this EDA company. They have over 100 tapeouts. They have a $28M in funding. They have 250 people. And you’ve never heard of them. Or at least I hadn’t.
They are ICScape. They started in 2005 with an investment from Acorn Campus Ventures and delivered their first product, ClockExplorer, in 2007 and their… Read More
There is a famous quote (probably attributed to Mark Twain who gets them all by default) “When looking for faults use a mirror not a spyglass.” Of course if you have RTL of your IP or your design then using a SpyGlass is clearly the better way to go. But it is getting even better since there is a new enhanced release, SpyGlass… Read More
When the name synonymous with personal computer graphics decided to turn their engineering talent toward the mobile business, heads turned. NVIDIA has rather quickly gained a foothold in tablets by squeezing four high performance processing cores, twelve graphics cores, and more onto a Tegra 3.… Read More
One year ago activist investor Carl Icahn started a hostile takeover bid for Mentor Graphics and was able to offer up three new board members, however yesterday we read that Mentor Graphics will:
While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.… Read More
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