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Synopsys-Springsoft: Almost Done

Synopsys-Springsoft: Almost Done
by Paul McLellan on 09-19-2012 at 8:01 am

 Synopsys announced today that they had completed the two main hurdles to acquiring SpringSoft. Remember, SpringSoft is actually a public Taiwanese company so has to fall in line with Taiwanese rules. The first hurdle is that they have obtained regulatory approval in Taiwan for the acquisition (roughly equivalent to FTC approval in the US, I think). And second, over 51% of the outstanding shares of SpringSoft have been tendered (roughly equivalent to voting in favor of the merger: once 51% shares have been tendered then Synopsys has to purchase the remaining shares and take over the company). Synopsys expects the deal to close definitively on October 1st next week.

UPDATE: actually Synopsys contacted me to point out that the deal doesn’t actually close on October 1st. They will take control of SpringSoft on that date and will start to consolidate SpringSoft financials into Synopsys financials. The deal will technically close later.

Springsoft has two product lines that are completely separate except sometimes being purchased by the same company.

The Laker (Laker[SUP]3[/SUP] is the latest version) product line is a layout editor with a lot of advanced analog placement and routing capability. Synopsys already had a layout capability. Then they bought Magma who had another, reputedly better one. Then they bought Ciranova who had a well-regarded analog placer. Now with SpringSoft they have yet another. I have no idea which technology will survive or how they will merge all this in the end.

The Verdi (Verdi[SUP]3[/SUP] is the latest version) product line is for functional verification. SpringSoft don’t have their own simulation capabililty but Verdi allows you to manage the verification process and analyze results. Synopsys also have verification environments (not to mention simulators). Again, over time, presumably these technologies will be merged.

They also have some interesting FPGA-based technology called ProtoLink. This allows FPGA-based verification to be done much more effectively by being able to change which signals are probed on the fly without needing to recompile the entire netlist, which for a big design is very slow. I don’t think Synopsys have anything like it.


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