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Apple Plays Saudi Arabia’s Role in the Semiconductor Market

Apple Plays Saudi Arabia’s Role in the Semiconductor Market
by Ed McKernan on 09-27-2011 at 12:08 am

The retirement of Steve Jobs left most commentators wondering if Tim Cook could lead Apple marching ever onward and upward. In truth, Tim Cook’s contribution on the operations side has been just as instrumental in the destruction of Apple’s PC and consumer electronics competitors as Jobs’ product vision. Under Tim Cook’s guidance,… Read More


Semiconductor equipment spending beginning to decline

Semiconductor equipment spending beginning to decline
by Bill Jewell on 09-25-2011 at 7:41 pm

Semiconductor manufacturing equipment shipments have leveled off after a strong rebound from the 2008-2009 downturn. August 2011 three-month-average shipments based on combined data from SEMI (North American and European companies) and SEAJ (Japanese companies) were $2.9 billion, down from a peak of $3.2 billion in May Read More


A Verilog Simulator Comparison

A Verilog Simulator Comparison
by Daniel Payne on 09-22-2011 at 2:40 pm

Intro
Mentor, Cadence and Synopsys all offer Verilog simulators, however when was the last time that you benchmarked your simulator against a tool from a smaller company?

I just heard from an RTL designer (who wants to remain anonymous) about his experience comparing a Verilog simulator called CVC from Tachyon against ModelSim… Read More


Apple’s Supply Chain

Apple’s Supply Chain
by Paul McLellan on 09-21-2011 at 5:48 pm

I am doing some consulting right now for a company that shall remain nameless, and one of the things I have had to look at is Apple’s supply chain. I came across an interesting article by someone with the goal to “buy a MacBook Air that isn’t made by Apple.” He is in the UK and doesn’t like Apple’s… Read More


Custom Signal Planning Methodologies

Custom Signal Planning Methodologies
by Paul McLellan on 09-20-2011 at 4:08 pm

It is no secret that custom ICs are getting larger and more complex and this has driven chip design teams to split up into smaller teams to handle the manual or semi-automated routing of the many blocks and hierarchical layers that go to make up such a design. These sub-teams don’t just need to handle the routing within their own block(s)… Read More


Analog Constraint Standards

Analog Constraint Standards
by Paul McLellan on 09-20-2011 at 8:00 am

Over the years there has been a lot of standard creation in the IC design world to allow interoperability of tools from different vendors. One area of recent interest is interoperable constraints for custom IC design. Increasingly, analog design layout is becoming more automated. Advanced process nodes require trial layouts… Read More


Coby Hanoch joins Jasper

Coby Hanoch joins Jasper
by Paul McLellan on 09-20-2011 at 7:00 am

Jasper has hired Coby Hanoch as the VP of international sales to manage sales outside of North America. I talked to him last week.

Coby started his career after graduation from the Israeli Institute of Technology as an engineer at National Semiconductor. He quickly ended up in verification where they developed the first random … Read More


Nanometer Circuit Verification: The Catch-22 of Layout!

Nanometer Circuit Verification: The Catch-22 of Layout!
by Daniel Nenni on 09-19-2011 at 8:00 pm

As analog and mixed-signal designers move to very advanced geometries, they must grapple with more and more complex considerations of the silicon. Not only do nanometer CMOS devices have limitations in terms of analog-relevant characteristics such gain and noise performance, but they also introduce new sources of variation… Read More


AMS Design, Optimization and Porting

AMS Design, Optimization and Porting
by Daniel Payne on 09-19-2011 at 2:35 pm

AMS design flows can follow a traditional path or consider trying something new. The traditional path goes along the following steps:
[LIST=1]

  • Design requirements
  • Try a transistor-level schematic
  • Run circuit simulation
  • Compare the simulated results versus the requirements, re-size the transistors and go back to step 3 or
  • Read More

    PVT and Statistical Design in Nanometer Process Geometries

    PVT and Statistical Design in Nanometer Process Geometries
    by Daniel Nenni on 09-18-2011 at 9:00 am

    On Sept 22, 2011, the nm Circuit Verification Forumwill be held in Silicon Valley, hosted by Berkeley Design Automation. At this forum, Trent McConaghy of Solido DA will present a case study on the TSMC Reference Flow 2.0 VCO circuit, to showcase Fast PVT in the steps of extracting PVT corners, verifying PVT, and doing post-layout… Read More