Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC InnovationToday Alchip Technologies, a Taipei-based leader in high-performance…Read More
WEBINAR: Functional ECO Solution for Mixed-Signal ASIC DesignThis webinar, in partnership with Easy-Logic Technology, is…Read More
Beyond Von Neumann: Toward a Unified Deterministic ArchitectureBy Thang Tran For more than half a…Read More
Intel Unveils Clearwater Forest: Power-Efficient Xeon for the Next Generation of Data CentersAt the recent Hot Chips conference, Intel® unveiled…Read More
Two Perspectives on Automated Code GenerationIn engineering development, automated code generation as a…Read More
ARM TechCon Software and Systems Keynote: Why Ultra-Low Power Computing Will Change Everything Simon Segars, speaking of the importance of continuing low power initiatives, introduced Dr. Jonathan Koomey, Consulting Professor at Stanford. (First impression, our kind of guy: He wears engineer shoes, not sales shoes!)
Koomey… Read More
At CES 2011, Steven Sinofsky of Microsoft stepped on the stage and went off the map of proven Windows territory. Announcing the next version of Windows would support the ARM Architecture, including SoCs from Qualcomm, NVIDIA, and TI, set a new course for Microsoft.
But Windows, being the battleship-sized behemoth that it is, would… Read More
An announcement at the ARM conference was of a joint project to tape out an ARM Cortex-M0 in IBM’s 14nm FinFET process. In fact they taped out 3 different versions of the chip using different routing architectures to see the impact on yield.
This was the first 14nm ARM tapeout, it seems. I’m sure Intel has built plenty … Read More
AMD announced yesterday that they would be building 64-bit ARM-based chips intended for use in servers. What was unclear is what the processors would be like. Although ARM had announced that they would move into 64-bit processors they didn’t have any that they had actually announced as being available for licensing.
At … Read More
FPGA Prototyping is growing in popularity as a method to get an SoC design into hardware running at clock speeds up to 100MHz or so. One downside during traditional FPGA prototyping debug is the limited number of internal signals that you can observe while trying to chase down bugs in the hardware design in the presence of running … Read More
I’ve talked before about how Apple and Samsung make most of the money in the handset business (and also about how Nokia…er…doesn’t). Now there is a report from Canaccord Genuity makes it clear just how much of the profit they make: 106%. And that is down from second quarter when they made 108%.
How can they… Read More
Jasper restructured JasperGold so that it could deliver its formal technology more flexibly by having a base system and a porfolio of apps. This would also make it easier to upgrade capabilities by creating new apps. Today, Jasper announced two new apps:
A funny thing happened at dinner the other night. The SemiWiki blog “8 Things I Hate about My iPhone5” caused quite a discussion. Half the table had Samsung phones and the other half iPhones. It really was more of a religious or political debate versus a rational consumer electronic discussion. An interesting side note, it seems … Read More
At DAC in June I visited and blogged about 30+ EDA and Semi IP companies, however I didn’t have time to watch the TowerJazz presentation in the Cadence Theater entitled: AMS Flow for Power Management Designs. Today I watched the 26 minute video and have summarized what I learned in this blog post.… Read More
“Simulation: Expert Insights into Modeling Microcontrollers” was the recent panel hot topic at Renesas DevCon2012, featuring Paolo Giustoof GM, Mark Ramseyerof Renesas, Marc Serughettiof Synopsys, Jay Yantchevof ASTC / VWorks, and Simon Davidmannof Imperas.
… Read More
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Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs