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Deploying 14nm FinFETs in your Next Mobile SoC

Deploying 14nm FinFETs in your Next Mobile SoC
by Daniel Payne on 06-19-2013 at 11:05 am
Categories: EDA, FinFET, Foundries, GlobalFoundries, Synopsys

At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.

Panelists included:

… Read More
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Is Your Synchronizer Doing its Job (Part 1)?

Is Your Synchronizer Doing its Job (Part 1)?
by Jerry Cox on 06-18-2013 at 8:30 pm
Categories: EDA

Recently, I discussed the increasing risk of metastability hazards at nanoscale geometries. These risks are significantly aggravated at low supply voltages and low temperatures and must be addressed during the design cycle of any mission critical application. This time I discuss what it takes to estimate a synchronizer’s … Read More

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Derivative Designs Need Tools Too

Derivative Designs Need Tools Too
by Paul McLellan on 06-18-2013 at 11:58 am
Categories: EDA

Increasingly, SoC designs consist of assembling blocks of pre-designed IP. One special case is the derivative design where not just the IP blocks get re-used but a lot of the assembly itself. For example, in the design below some blocks are added, some blocks are updated, some hierarchy is changed. But the bulk of the design remains… Read More

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Increasing Automotive Semiconductor Test Quality

Increasing Automotive Semiconductor Test Quality
by glforte on 06-17-2013 at 4:45 pm
Categories: EDA, Siemens EDA

The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. At the same time, traditional fault models are becoming less effective at achieving desired silicon quality levels. Improvements in test solutions are needed… Read More

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Formality Ultra, Streamline Your ECOs

Formality Ultra, Streamline Your ECOs
by Paul McLellan on 06-17-2013 at 8:00 am
Categories: EDA, Synopsys

One of the most challenging stages in an SoC design is achieving timing closure. Actually design closure is perhaps a better term since everything needs to come together such as clock tree, power nets, power budget and so on. Changes made to the design are known as ECOs (which stands for engineering change orders, a term that comes… Read More

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Taiwan Semiconductor Tries To Pull A FinFAST One!

Taiwan Semiconductor Tries To Pull A FinFAST One!
by Daniel Nenni on 06-16-2013 at 7:00 pm
Categories: Foundries, TSMC


This completely misleading title is from a Seeking Alpha (SA) article, a stock investment version of the National Enquirer. As I mentioned inA Call to ARMs, fame and fortune seeking SA Authors make a penny per click so sensationalism sells. The article is not worth your time so I will save you the click and skip to the misguided conclusion:… Read More

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Should You Buy All Aspects of Your IP From a Single Supplier?

Should You Buy All Aspects of Your IP From a Single Supplier?
by Paul McLellan on 06-16-2013 at 9:18 am
Categories: Arasan, IP

Interface IP typically consists of multiple layers, most importantly a PHY (level 1) analog (or mixed signal) block that handles the interface to the outside world and a number of levels of digital controllers. The interfaces between all these levels, especially between the PHY and the controller, is often defined by the interface… Read More

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Swap and Play Extended To Chip Fabric and Memory Controllers

Swap and Play Extended To Chip Fabric and Memory Controllers
by Paul McLellan on 06-16-2013 at 9:08 am
Categories: Arteris, Cadence, EDA, IP

Virtual platforms enable software development to take place on a model of an electronic system. What everyone would like is models that are fast and accurate but that is simply not possible. Fast models are fast because they don’t model everything at the signal level. And accurate models get to be accurate by handling a lot of detail… Read More