David Abercrombie from Mentor Graphics met with me on Tuesday at DAC to provide an update on DPT – Double Patterning Technology, something new required for several layers starting at the 20nm node in order to get any IC yield. DPT is also part of Multiple-Patterning.… Read More
Custom IC Layout Automation at DAC
Three people from Ciranova met with me at DAC this year: Eric Filseth (CEO), David Millman (Marketing) and Lindor Hendrickson (CTO). They gave me an update on how the Helix tools are being used to automate the layout of custom IC designs at 28nm and smaller nodes.… Read More
IPL Alliance at DAC
Lunch on Tuesday at DAC was sponsored by the IPL Alliance and thankfully this year they skipped the attempt at humor and focused on interoperable PDKs. Presenting companies include: Synopsys, Dongbu HiTek, TowerJazz, X-FAB and Si2. Having both OpenPDK and iPDK on the same platform does sound like a peaceful co-existence to me,… Read More
Tensilica: We are #2 so we try harder
The Linley group is the go-to source for information about the microprocessor market. If you go back to their roots in Michael Slater’s Microprocessor Report then they have been in the business for 25 years. We haven’t had microprocessors for that much longer. They just tagged Tensilica as being second in shipments… Read More
Atrenta Aquires NextOp
Atrenta announced today that it is acquiring NextOp Software. NextOp sells a tool BugScope that provides assertion synthesis technology. This complements Atrenta’s SpyGlass products for improving the process for design of complex semiconductor IP and SoCs.
I went to Atrenta’s office to talk to Ajoy Bose (CEO)… Read More
Shape-based IC Routing at DAC
IC place and route is a big challenge so we see many EDA companies creating tools. On Tuesday at DAC I met with Dave Noble of Pulsic to get an update.
Notes
Dave Noble, VP Operations (EDA since 2003), Sperry Univac since 1974
– had been an EDA distributor for Pulsic as well
More leads qualified on Monday than all days of last year … Read More
3D Thermal and Mechanical Stress for IC Packaging
3D has been a growing buzz word in IC design and packaging for several years now, so it’s refreshing to actually find an EDA vendor that has developed tools to help analyze something like 3D thermal and mechanical stress at DAC. … Read More
Executive Opinion: The Future of EDA is Bright
The days following a major conference like DAC are a good time to reflect on the overall health and vibrancy of the electronic design automation (EDA) industry. I’ve been in EDA for 21 years and built two successful startups, and over the last couple of years, have witnessed some decline in both new talent and in venture investment… Read More
It takes an act of Congress…
Foreign students earn roughly two-thirds of the total engineering Ph.D.s earned in the U.S., yet there is no policy to allow, let alone encourage, them to stay in the U.S. after graduation. I was aware of this problem 14 years ago when I started working in EDA, but haven’t paid much attention since then.
So, I scoured the congressional… Read More
Selecting Non Volatile Memory IP: dynamic programming from Novocell Semiconductor lead to a lower “Cost Of Ownership”
NVM IP offering from NovocellSemiconductor is based on SmartBit, an antifuse, One Time Programmable (OTP) technology, and the OTP block are embedded in standard Logic CMOS without any additional process or post process steps and can be programmed at the wafer level, in package, or in the field, as end user requires. What makes … Read More
AI Semiconductor Market