New Cooling Strategies for Future ComputingPower densities on chips increased from 50-100 W/cm2…Read More
DAC News – proteanTecs Unlocks AI Hardware Growth with Runtime MonitoringAs AI models grow exponentially, the infrastructure supporting…Read More
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A Quick Look at Agentic/Generative AI in Software EngineeringAgentic methods are hot right now since single…Read More
“Innovations for Next Generation Scaling”
The 2013 Forum today (Feb 5, 2013) started with a presentation by Dr. Gary Patton, VP, IBM Semiconductor Research & Development Center. Gary very clearly articulated the two irresolvable challenges the industry now faces:
These … Read More
After a show like DesignConwraps up we get a chance to ask ourself what it all meant, and how was this year different than last year. Reading through many posts about DesignCon I came to discover that the Awards at DesignCon are less contentious than at CES, and also that ANSYSreceived a DesignVision awardfor the 2nd year running. … Read More
When I started in this business, we were at 3 micron HMOS. A few other things are close to that size. A red blood cells is about 9 microns, a human hair is about 100 microns. And in a bizarre “only in Japan” video, people compete to plane the thinnest shaving off a plank of wood. It turns out the answer is 9 microns. That’s… Read More
If you are considering filing a patent, you should know about the new patent rules effectinve on March 16, 2013. Most importantly, patent rights will switch from “first-to-invent” to “first-to-file.” Before we continue, I am not a lawyer; I’m just a dumb blogger. Seek actual legal advice about the new patent laws if you think… Read More
The numbers are starting to come in for how everyone did in Q4. According to Cannacord Genuity, Apple made 69% of the profit and Samsung made 34%. What do you notice about those numbers? They add up to more than 100%. HTC supposedly made 1% of the profit and everyone else either broke even or lost money. Basically Apple and Samsung have… Read More
So what is a silicon nanowire? It is basically a FET where the active element is a wire 3-20nm in diameter. So where a FinFET has the gate wrapped around 3 sides of the transistor, a nanowire (NW) has it wrapped around all four. In essence, the wire runs through the middle of the gate.
There seem to be three issues about building a silicon… Read More
The most interesting session at the Linley Tech Data Center Conference last week was the last one, on Designing Power Efficient Servers. What this was really about was whether ARM would have any success in the server market and what Intel’s response might be.
Datacenters are now very focused on power efficiency and many track… Read More
FinFETs are hot, carbon nanotubes are cool, and collaboration is the key to continued semiconductor scaling. These were the main messages at the 2013 Common Platform Technology Forum in Santa Clara.
The collaboration message ran through most presenations, like the afternoon talk by Subi Kengeri of GLOBALFOUNDRIES and Joe Sawicki… Read More
I was at the Common Platform Technology Forum this week. One of the most interesting sessions is IBM’s Gary Patton giving an overview of the state of semiconductor fabrication. Then, at lunchtime, he is one of the people that the press can question. In this post, I’m going to focus on Extreme Ultra-Violet (EUV) lithography.… Read More
The most exciting EDA + Semi IP company that I ever worked at was Silicon Compilers in the 1980’s because it allowed you to start with a concept then implement to physical layout using a library of parameterized IP, the big problem was verifying that all of the IP combinations were in fact correct. Speed forward to today and our… Read More
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