Linear pluggable optics target data center energy savingsData center density continues growing, driving interconnect technology…Read More
Bird’s Eye View Magic: Cadence Tensilica Product Group Pulls Back the CurtainEven for experienced technologists some technologies can seem…Read More
Siemens EDA Offers a Comprehensive Guide to PCIe® Transport SecurityIt is well-known that there is more data…Read More
The High Tech Trial of this Century: Apple vs. Samsung may end up being the catalyzing event that advances the established PC Monopolists known as Wintel (Microsoft and Intel) into leadership positions in the new era known as the Mobile Tsunami. Not a chance you say? Consider that the Apple, Samsung War is one that will not be settled… Read More
Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.
One of the tools in the Cadence… Read More
Josefina Hobbs, a solutions architect at Synopsys, shows the integration of Synopsys Protocol Analyzer with SpringSoft’s Verdi using the Verdi Interoperability Apps (VIA) which gives open access to the Verdi KDB and FSDB databases. She also demonstrates protocol debug made easy using the Protocol Analyzer. This gives… Read More
In April I blogged about using the iPad for schematic capture and SPICE circuit simulation. My conclusion was that the technology was interesting but not quite ready for commercial use. Today I tried out the web-based version using my Google Chrome browser instead of the iPad. Install the Chrome app here or visit www.ischematic.com… Read More
Even though most of us have witnessed the emergence of the fabless semiconductor industry it is still good to go back and remember how we got to where we are today, to realize that the semiconductors that you now hold in your hand were enabled by the rise of the fabless semiconductor business model. This is the first in a series of blogs… Read More
Consolidation continues in the EDA industry with Synopsys announcing today that they acquired Ciranova, a provider of software to automate custom IC layout. Remember that Synopsys invested in Ciranova back in March 2008 and September 2010 (along with Intel Capital, Mentor Graphics and Alloy Ventures), so this deal has some … Read More
Not yet a year into Rory Read’s term and the AMD board must be considering that the value of the x86 patents and engineering talent is worth much more than the stocks $3B valuation and easier to fathom putting on the auction block than continuing to sell $25 processors into the back channels of China and the Developing World. As I read… Read More
The SystemVerilog standard defines an X as an “unknown” value which is used to represent when simulation cannot definitely resolve a signal to a “1”, a “0”, or a “Z”. Synthesis, on the other hand, defines an X as a “don’t care”, enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often… Read More
The Wi-Fi Alliance is an industry consortium dedicated to driving adoption of the various Wi-Fi standards which also go under the rather less catchy name of IEEE 802.11x (where the x varies depending on the generation of the standard, right now a, b, g or n). They also certify devices for interoperability.
Wi-Fi Alliance says that… Read More
About 4 years ago some of my semiconductor cohorts urged me to blog. “Hey Dan, you’re a funny guy, write about EDA and IP, make us laugh!” Of course what I think is funny most people think is snarky, which is a nice word for being a smart ass. The traditional semiconductor press was crumbling, the non traditional EDA websites were outdated,… Read More
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