Rethink Scoreboards to Supercharge AI-Era CPUsBy Dr. Thang Minh Tran, CEO/CTO Simplex Micro…Read More
Jitter: The Overlooked PDN Quality MetricBruce Caryl is a Product Specialist with Siemens EDA…Read More
CEO Interview with Vamshi Kothur, of Tuple TechnologiesIt was my pleasure to meet with Vamshi…Read More
Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCsWhat if you could reduce power and extend…Read More
Reachability in Analog and AMS. Innovation in VerificationCan a combination of learning-based surrogate models plus…Read More
Atrenta today announced Dr Ajith Pasqual, who is the Head of the Department of Electronic & Telecommunication Engineering at the University of Moratuwa in Sri Lanka (which used to be known as Ceylon) has joined Atrenta’s technical advisory board (TAB). OK, academics join EDA company’s TABs all the time so that’s… Read More
There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start – is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger… Read More
It’s a classic and creative example of design and EDA tool community getting together, exploiting tool capabilities and developing flows which add value to all stake holders including the end consumer. We know power has become extremely important for battery life in smart phones, high performance servers, workstations, notebooks… Read More
If you want to know the state of play in lithography, there is no better place than the special session on lithography at Semicon West. This year was no exception. The session was given the punchy title Still a tale of 2 paths: multi-patterning lithography at 20nm and below: EUVL source and infrastructure progress.
In the blue corner… Read More
VLSI’s business grew healthily but it never threw off enough cash to fund all the investment required for process technology development and capital investment for a next generation fab. They made a strategic partnership with Hitachi covering both 1um process technology and a significant investment, which meant that … Read More
There is a new book out from Springer. The subtitle is actually a better description that the title. The subtitle is A Practical Guide to Synopsys Design Constraints (SDC) but the title isConstraining Designs for Synthesis and Timing Analysis. The authors are Sridhar Gangadharan of Atrenta in San Jose and Sanjay Churiwala of Xilinx… Read More
Trying to trace DSP birth as a standard IC product, you come back to the early 80’s, when a certain Computer manufacturer named IBM has asked to a certain Semi-Conductor giant (at that time) named Texas Instruments if they could turn a lab concept, Digital Signal Processor, into a standard product that IBM could buy to TI, like they… Read More
If you have purchased a high-end cell-phone or tablet in the last couple of years it probably has LTE, although some carriers try and blur things by showing a symbol like 4G when you are in an area that has LTE despite the fact that your phone does not support it. Don’t you love cell-phone marketing? Talking of which, if a camel … Read More
The future growth in smartphones is largely going to be at the low end of the market as Eric wrote about here a couple of weeks ago. A lot of that growth is targeted at China. Sitting in the US it is easy to underestimate the size of the Chinese market. China Mobile (the market leader) is just one company but has more than twice the number … Read More
Two videos (both short) from Qualcomm. They are both amusing but also have a serious aspect to them. The first one is interesting since it is Qualcomm following in Intel’s footsteps with its “Intel Inside” campaign against AMD to make people care about what processor was in their PC. Until that point probably… Read More
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Facing the Quantum Nature of EUV Lithography