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Spectre from Cadence Goes FastSPICE

Spectre from Cadence Goes FastSPICE
by Daniel Payne on 10-09-2013 at 2:31 am

Transistor-level circuit designers have an insatiable appetite to run numerous SPICE circuit simulations in order to determine circuit speed, current and power across Process, Voltage and Temperature (PVT) conditions. Just look at the number of PVT corners increasing as the technology nodes go to 16nm:

The good news today … Read More


Managing Multi-site Design with Cliosoft at LBNL

Managing Multi-site Design with Cliosoft at LBNL
by Paul McLellan on 10-08-2013 at 11:40 pm

With the award of the Nobel prize for physics to Higgs (who used to work in the same building at Edinburgh as I did, reflected glory) and Englert yesterday, CERN has been in the news. ClioSoft has an interesting presentation given at CERN about designing a detector chips. The work was done two or three years ago, managed from Lawrence… Read More


Can you Publicly Benchmark EDA Tools?

Can you Publicly Benchmark EDA Tools?
by Daniel Nenni on 10-08-2013 at 7:00 pm

There is an interesting discussion on SemiWiki in regards to the age old question aboutbenchmarking EDA tools. I remember benchmark discussions at my first DAC in 1984. It was deemed impossible to do a “fair” public benchmark then and it’s not possible now, just my opinion of course but let me tell you why. Simply stated it is a legal,… Read More


Mentor Seminar: Evolution of diagnosis-driven yield analysis

Mentor Seminar: Evolution of diagnosis-driven yield analysis
by Beth Martin on 10-08-2013 at 1:20 pm

It’s a fact that new process nodes come with some amount of yield challenges. One way to find and eliminate silicon defects is through diagnosis-driven yield analysis (DDYA), which is the topic of a free seminar by Mentor Graphics in Fremont this Thursday, October 10 from 11:30am – 2pm (yes, lunch is included because Mentor… Read More


Atrenta Japan Technoloogy Forum

Atrenta Japan Technoloogy Forum
by Paul McLellan on 10-08-2013 at 12:27 am

As they have done for the last few years, Atrenta held its fifth annual user group meeting at the Shin Yokohama Kokusai Hotel on September 13. The attendees are a mixture of customers and other interested members of the semiconductor supply chain. There were nearly 90 people there representing 48 different companies in Japan.

The… Read More


Cadence’s System-to-Silicon Verification Summit

Cadence’s System-to-Silicon Verification Summit
by Randy Smith on 10-06-2013 at 6:00 pm

At this year’s DAC, I spoke with several friends at Cadence. I got the distinct impression that something at Cadence had changed. There was a sense of pride and accomplishment that it seems to me had drifted away over the years. Now employees were speaking with true conviction about the accomplishments of the product development… Read More


A Big Thank You to EDA and IP

A Big Thank You to EDA and IP
by Daniel Nenni on 10-05-2013 at 10:00 pm

Electronic Design Automation Software and Semiconductor Intellectual Property are not so much the tail that wags the dog, rather they are like the heart of an elephant, tiny in comparison but without which there is no elephant. There is no doubt that EDA and IP have been key enablers of the semiconductor industry for the past 50 years… Read More


Synopsys: Getting To Know EDA’s Heavyweight Champion

Synopsys: Getting To Know EDA’s Heavyweight Champion
by Ashraf Eassa on 10-05-2013 at 8:00 pm

From chip IP vendor ARM Holdings to semiconductor foundry Taiwan Semiconductor, there have been many winners from the mobile device revolution that was sparked by Apple’s introduction of the iPhone. However, while these big-ticket names get all the fame and glory, the electronic design automation space (“EDA” for short) is … Read More


High resolution Analog CMOS IC Design

High resolution Analog CMOS IC Design
by Daniel Payne on 10-04-2013 at 5:02 pm

My background includes transistor-level IC design, so I take delight in talking with engineers like Dr. Lanny Lewyn that are still practicing the art and science of analog IC design. Dr. Lewynis a Life Senior Member of the IEEE and has a consulting business. If you live in Santa Clara, then consider attending a live seminar on OctoberRead More


TSMC OIP 2013 Trip Report!

TSMC OIP 2013 Trip Report!
by Daniel Nenni on 10-04-2013 at 4:00 pm

The 5[SUP]th[/SUP] annual TSMC OIP Forum was last week and thankfully there were no surprises with the exception of how many people asked me who I think will be the next TSMC CEO. Certainly I have no idea but I would be happy to use my incredible powers of deductive reasoning to determine who it will be.

The TSMC Open Innovation Platform®Read More