800x100 Webinar (1)

10 years, 100,000 miles, or <1 DPM

10 years, 100,000 miles, or <1 DPM
by Don Dingee on 05-30-2013 at 10:00 pm

Auto makers have historically been accused of things like planned obsolescence – redesigning parts to make repairs painfully or even prohibitively expensive – and the “warranty time-bomb”, where major systems seem to fail about a week after the warranty expires. Optimists would chalk both those up to relentless innovation,… Read More


SEMulator3D – A Virtual Fab Platform

SEMulator3D – A Virtual Fab Platform
by Pawan Fangaria on 05-30-2013 at 8:30 pm

Yes, it’s a pleasant surprise; it is Virtual Fabrication Platform, one of the new innovations in 2013. I was looking around for what kind of breakthrough technologies will be announced in DAC this year. And here I came across this new kind of innovative tool which can produce final virtual fabricated 3D structures after following… Read More


You can tune a piano, but you can’t tune a cache without help

You can tune a piano, but you can’t tune a cache without help
by Don Dingee on 05-30-2013 at 8:30 pm

Once upon a time, designing a product with a first generation SoC on board, we were trying to use two different I/O peripherals simultaneously. Seemed simple enough, but things just flat out didn’t work. After days spent on RTFM (re-reading the fine manual), we found ourselves at the absolute last resort: ask our FAE.

After about… Read More


DAC lunch seminar: Better IP Test with IEEE P1687

DAC lunch seminar: Better IP Test with IEEE P1687
by Beth Martin on 05-30-2013 at 7:28 pm

What: DAC lunch seminar (register here)
When: June 5, 2013, 11:30am – 1:30pm
Where: At DAC in lovely Austin, TX

Dr. Martin Keim of Mentor Graphics will present this overview of the new the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG.

If you are involved in IC test*, you’ve probably heard about IJTAG. If you … Read More


NanGate Launches Aggressive DAC Campaign: 50 Library Characterization Licenses for USD 50K

NanGate Launches Aggressive DAC Campaign: 50 Library Characterization Licenses for USD 50K
by Daniel Nenni on 05-30-2013 at 12:00 pm

NanGate today announced a very aggressive “50-50 campaign”. Throughout June and July and in celebration of DAC 50th anniversary, NanGate will be offering 50 licenses of its Library Characterizer™ product for USD 50K for the first year. The offer applies to new customers as well as to existing customers that do not yet license the… Read More


TSMC ♥ Berkeley Design Automation

TSMC ♥ Berkeley Design Automation
by Daniel Nenni on 05-30-2013 at 11:00 am

As I mentioned in BDA Takes on FinFET Based Memories with AFS Mega:

Is AFS Mega real? Of course it is, I’m an SRAM guy and I worked with BDA on this product so I know. But don’t take my word for it, stay tuned for endorsements from the top SRAM suppliers around the world.

Here is the first customer endorsement from the #1 foundry.… Read More


2013 semcionductor market forecast lowered to 6% from 7.5%

2013 semcionductor market forecast lowered to 6% from 7.5%
by Bill Jewell on 05-30-2013 at 9:00 am

The global semiconductor market was weaker than expected in 1Q 2013, down 4.5% from 4Q 2012 according to WSTS. Much of the softnes was attributable to a major falloff in the PC market. According to International Data Corporation (IDC), 1Q 2013 PC shipments were down 15% from 4Q 2012 and down 14% from 1Q 2012. Other key end markets remained… Read More


Atrenta: Mentor/Spyglass Power Signoff…and a Book

Atrenta: Mentor/Spyglass Power Signoff…and a Book
by Paul McLellan on 05-30-2013 at 7:00 am

Today Atrenta and Mentor announced that they were collaborating to enable accurate, signoff quality power estimation at the RTL for entire SoCs. The idea is to facilitate RTL power estimation for designs of over 50M gates running actual software loads over hundreds of millions of cycles, resulting in simulation datasets in the… Read More


Efficient Handling of Timing ECOs

Efficient Handling of Timing ECOs
by Daniel Nenni on 05-29-2013 at 8:00 pm

Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancing… Read More