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Using HLS to Turbocharge Verification

Using HLS to Turbocharge Verification
by Paul McLellan on 10-16-2013 at 8:23 am

One of the benefits of using high-level synthesis is obviously the ease of writing some algorithms in SystemC since it is at a higher level than RTL (that’s why we call it high-level synthesis!). But a second benefit is at the verification level. Since a lot of the verification gets done at the SystemC level, less needs to be done at the RTL level.

The SystemC designs used in an HLS flow typically simulate 100-1,000 times faster than RTL. This is because the interfaces and timing are specified in an abstract source. So verification done at the SystemC level is a lot more efficient than waiting until the RTL level (or having no option if you are not using HLS, since RTL will then be all you have).

UPDATE: webinar moved to November 5th

Calypto have a webinar on just this topic coming up next week. It is at 10am on Tuesday November 5th. The presenter is Bryan Bowyer who leads the product design team. Previously he was product manager for HLS at Mentor and has worked in the topic area for 13 years. The webinar is titled How to Maximize the Verification Benefit of High Level Synthesis with SystemC.

 In the 50 minute webinar, Bryan will describe a verification approach that leverages SystemC simulation and HLS to reduce the RTL verification effort by 50%. He will describe how to write a bit-accurate SystemC design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL level.

Catapult did well in Cooley’s DAC report (here) where a dozen people picked it as a “best of DAC”, a lot more than the competition. I’m a bit more wary than John is of reading anything into this type of pop quiz. People who go to DAC are already a biased sample (more from US, fewer from Japan and Europe, maybe a disproportionate number from Austin-based companies this year). Of the people who go to DAC, the people who send Cooley feedback is another small subset. But the comments from actual users are valuable. For example, one designer said:”I’ve had huge algorithms in SystemC and the RTL generated by Catapult simply PASSED in testbench verification FIRST time without any fixes!”

That is almost the perfect trailer for the webinar. Once again it is at 10am Pacific on November 5th. More details, including a link for registration, are here.

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