NanoSpice Pro X Webinar SemiWiki

Ansys Revving up for Automotive and 3D-IC Multiphysics Signoff at DAC 2023

Ansys Revving up for Automotive and 3D-IC Multiphysics Signoff at DAC 2023
by Daniel Nenni on 06-26-2023 at 10:00 am

dac 2023 600x100

 

Highlights:

  • Ansys CTO Prith Banerjee will be delivering the Visionary Speaker opening address on Tuesday 11th
  • There will be technical presentations every hour in the Ansys Booth Theater (#1539)
  • Get yourself a complimentary sit-down breakfast and a discussion on automotive electronics by registering for the Ansys DAC
Read More

Assessing EUV Wafer Output: 2019-2022

Assessing EUV Wafer Output: 2019-2022
by Fred Chen on 06-26-2023 at 6:00 am

Assessing EUV Wafer Output 2019 2022

At the 2023 SPIE Advanced Lithography and Patterning conference, ASML presented an update on its EUV lithography systems in the field [1]. The EUV wafer exposure output was presented and is shown below in table form:

From this information, we can attempt to extract and assess the EUV wafer output per quarter. First, since there … Read More


Podcast EP166: How iDEAL Semiconductor is Revolutionizing Power Device Design & Manufacturing

Podcast EP166: How iDEAL Semiconductor is Revolutionizing Power Device Design & Manufacturing
by Daniel Nenni on 06-23-2023 at 10:00 am

Dan is joined by Ryan Manack, Vice President of Marketing for iDEAL Semiconductor. Prior to iDEAL Ryan spent 15 years at Texas Instruments which I consider one of the most influential companies in the history of semiconductors.

Ryan describes SuperQ, the unique core technology platform of iDEAL Semiconductor. Using the approach… Read More


Efabless Celebrates AI Design Challenge Winners!

Efabless Celebrates AI Design Challenge Winners!
by Daniel Nenni on 06-23-2023 at 6:00 am

Efabless AI Challenge SemiWiki

The first AI Generated Open-Source Silicon Design Challenge invited participants to use generative AI to design an open-source silicon chip and tape it out in just three weeks. The contestants were required to create Verilog code from natural language prompts, and then implemented their designs using the chipIgnite platform… Read More


Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges

Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges
by Nanette Collins on 06-22-2023 at 10:00 am

CEO Outlook #2

Chances are anyone who attended the CEO Outlook will say it was an engaging, entertaining and enlightening view of the chip design space, though CEO Outlook may be a misnomer as four of the seven panelists had C-Suite titles other than CEO.

Regardless, the collective view was optimistic, though caution prevailed as the economic… Read More


Tensilica Processor Cores Enable Sensor Fusion For Robust Perception

Tensilica Processor Cores Enable Sensor Fusion For Robust Perception
by Kalar Rajendiran on 06-22-2023 at 6:00 am

Tensilica DSPs

While sensor-based control and activation systems have been around for several decades, the development and integration of sensors into control systems have significantly evolved over time. Early sensor-based control systems utilized basic sensing elements like switches, potentiometers and pressure sensors and were … Read More


Intel Internal Foundry Model Webinar

Intel Internal Foundry Model Webinar
by Scotten Jones on 06-21-2023 at 12:00 pm

IAO Investor Webinar Slides to post on our INTC website PDF Page 07

Intel held a webinar today to discuss their IDM2.0 internal foundry model. On the call were Dave Zinsner Executive Vice President and Chief Financial Officer and Jason Grebe Corporate Vice President and General Manager of the Corporate Planning Group.

On a humorous note, the person moderating the attendee questions sounded … Read More


The Updated Legacy of Intel CEOs

The Updated Legacy of Intel CEOs
by Daniel Nenni on 06-21-2023 at 10:00 am

Intel HQ 2023

(First published December 24, 2014)

A list of the best and worst CEOs in 2014 was recently published. The good news is that none of our semiconductor CEOs were on the worst list. The bad news is that none of our semiconductor CEOs were on the best list either. I will be writing about the CEOs that made our industry what it is today starting… Read More


Managing Service Level Risk in SoC Design

Managing Service Level Risk in SoC Design
by Bernard Murphy on 06-21-2023 at 6:00 am

Traffic

Discussion on design metrics tends to revolve around power, performance, safety, and security. All of these are important, but there is an additional performance objective a product must meet defined by a minimum service level agreement (SLA). A printer display may work fine most of the time yet will intermittently corrupt the… Read More


DDR5 Design Approach with Clocked Receivers

DDR5 Design Approach with Clocked Receivers
by Daniel Payne on 06-20-2023 at 10:00 am

DFE min

At the DesignCon 2023 event this year there was a presentation by Micron all about DDR5 design challenges like the need for a Decision Feedback Equalizer (DFE) inside the DRAM. Siemens EDA and Micron teamed up to write a detailed 25 page white paper on the topic, and I was able to glean the top points for this much shorter blog. The DDR5… Read More