Success in a business with extended design-in cycles may look easy. In reality, there is a delicate balance between many factors. Some come to mind immediately: developing and releasing a good product in the first place; winning and keeping the right customers, not too few or too many; balancing investment between support and … Read More
CEO Interview with Dr. Naveen Verma of EnCharge AINaveen Verma, Ph.D., is the CEO and Co-founder…Read More
WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent DevicesEdge AI is rapidly transforming how intelligent solutions…Read More
How to meet 3Ps in 3D-ICs with sub-20nm Dies?
It feels to be at the top of semiconductor technology by having dies with high density of semiconductor design at sub-20nm technology node stacked together into a 3D-IC to form a complete SoC which can accommodate billions of gates. However there are multiple factors to be looked at in order to make that successful amid often conflicting… Read More
Calypto: the View From the Top
At DVCon today I talked to Sanjiv Kaul, the CEO of Calypto. Just as a reminder, Calypto have 3 products, SLEC (sequential logical equivalence checking, also called sequential formal verification), PowerPro (sequential RTL level power reduction) and Catapult High Level Synthesis (that they took over from Mentor in 2011 in a complicated… Read More
Automating PCB Timing Closure, Saving Up to 67%
The benefits of using EDA software is that it can automate a manual process, like PCB timing closure, saving you both time and engineering effort. This point was demonstrated today as Cadenceadded new timing-closure automation to their Allegroproduct family, calling it Allegro TimingVision. On Tuesday I spoke with Hemant Shah… Read More
450mm Delayed and Other SPIE News
Last week I attended the SPIE Advanced Technology Conference. There were a lot of interesting papers and as is always the case at these conferences, there was a lot of interesting things to learn from talking to other attendees on the conference floor.
The first interesting information from the conference floor was that 450mm is… Read More
What I Didn’t Know about Electronic Design Automation
I started using internal EDA tools at Intel beginning in 1978 and have worked in the commercial EDA industry since 1986, so it was a delight to read a chapter about EDA in Nenni and McLellan’s newest book: Fabless – The Transformation of the Semiconductor Industry. Starting in the 1970’s the authors talk about… Read More
Dr. Walden Rhines Vision on Semiconductor & India
Last month India Electronics & Semiconductor Association (IESA) held its Vision Summit at Bangalore in which luminaries from across the semiconductor and electronics industry presented their views about the future of this industry and India’s progress. Dr. Walden C. Rhines, Chairman and CEO of Mentor Graphicspresented… Read More
Synopsys Announces Verification Compiler
Integration is often an underrated attribute of good tools, compared to raw performance and technology. But these days integration is differentiation (try telling that to your calculus teacher). Today at DVCon Synopsys announced Verification Compiler which integrates pretty much all of Synopsys’s verification technologies… Read More
Does Multiprotocol-PHY IP really boost TTM?
I have often written in Semiwiki about high speed PHY IP supporting Interface protocols (see for example this blog), the SoC cornerstone, almost as crucial as CPU, GPU or SDRAM Memory Controller. When you architect a SoC, you first select CPU(s) and/or GPU(s) to support the system basic functionality (Processor for Mobile application,… Read More
ARM Lab in a Box
St. Francis Xavier said “Give me the child until he is seven and I’ll give you the man.” ARM is not going for them quite that young but this week they announced their “lab in a box” for participating universities worldwide. It is actually a joint launch between the ARM University Program (which is not new)… Read More
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