The traditional system-on-chip (SoC) design process has fully qualified verification methods embodied in the form of process design kits (PDKs). Why is it that chip design companies and assembly houses have no IC/package co-design sign-off verification process?
Package die are often produced using multiple processes and… Read More
Arm targets the agentic AI era with new edge, cloud and robotics platformsArm is expanding its computing platform for an…Read More
Rethinking AI Chips: How VSORA Redesigned the Hardware That Runs AIInstead of tweaking existing designs, VSORA built an…Read More
UWB Without the Integration Headache: Ceva and LG Bring Precision to More ChipsCeva and LG Electronics have joined forces to…Read More
PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI ConnectivityBy Tim Messegee, Senior Director of Solutions Marketing…Read More
Semiconductor Engineering Has a State-Continuity ProblemProduct realization depends not only on reaching the…Read MoreCadence 2015 Q2 Results
Let’s start by getting the financial stuff out of the way. Revenue was $416 million; non-GAAP operating margin was 28%; non-GAAP EPS was $0.27; and operating cash flow was $122 million (up at lot, it was just $47M in Q1 and $69M in Q2 of 2014).
The thing that the financial types are most interested in are the changes to Cadence’s… Read More
The Evolution of Smart Glass Design
The wearer says, “O.K., Glass” and glass leaps into action, performing most of the smartphone functions like check e-mails, take photos and videos, provide turn-by-turn navigation, and make and receive phone calls. Welcome to Smartphone 2.0.
Technology pundits called Google Glass the best thing that happened… Read More
The Antiportfolio
Last week Charlie Cheng of Kilopass wrote about venture capital for semiconductor. This reminded me of something amusing that I came across years ago.
See also VC For Semiconductor: Dead or Alive?
All VCs have a portfolio page and often a second exit page. The first shows the companies in which they currently hold investments and… Read More
UTBB SOI can scale down to 5nm says Skotnicki…
…and FinFET down to 3nm. This assertion is the result of extensive research work made by Thomas Skotnicki, ST Fellow and Technical VP, Disruptive Technologies, leading to numerous publications, like in 1988 in IEEE EDL or in 2008 in IEEE TED paper. I say extensive, I should also say long, very long, as it took almost 30 years for the… Read More
Semi Equip Stocks Roll Over & Play Dead? Semicon Post Partum Depression?
Are Semi Equipment Stocks & Industry Rolling Over?
Is there any Upside in the second half of 2015?
Waiting for next years iPhone 7 refresh?
Does Windows 10 even matter?
“Sell in May and Go Away”
An old investor’s adage that has proven correct this year. The Semiconductor Equipment stocks seemed to have had… Read More
Build Low Power IoT Design with Foundation IP at 40nm
In a power hungry world of semiconductor devices, multiple ways are being devised to budget power from system to transistor level. The success of IoT (Internet of Things) Edge devices specifically depend on lowest power, lowest area, optimal performance, and lowest cost. These devices need to be highly energy efficient for sustained… Read More
Ultra-low Power IP for Wearables
Wearables and the Internet of Things (IoT) in general are all about low power. Everyone must have read (or even experienced) the phenomenon of putting something like a Fitbit on and then after a short period leaving it in a drawer or putting it to recharge and forgetting about it for weeks. The longer devices can last the more likely… Read More
Designing an IDCT for H.265 using High Level Synthesis
Math geeks know all about Inverse Discrete Cosine Transforms (IDCT) and a popular use is in the hardware architecture of High Efficiency Video Coding (HEVC), also known as H.265, the new video compression standard and widely used in consumer and industrial video devices. You could go about hand-coding RTL to create an IDCT function,… Read More
6 Memory Considerations for IoT Designs Built Around Cortex-M7 MCUs
Tightly coupled memory (TCM) is a salient feature in the Cortex-M7 microcontrollers as it boosts the MCU performance by offering single cycle access for the CPU and by securing the high-priority latency-critical requests from the peripherals.… Read More


ASML Has High-NA and Chipmakers Can’t Say No