As the SoC design size, complexity and functionality keeps on increasing with multiple IPs packed together and design time and time-to-market keeps on decreasing amid critical constraints on PPA, there is no other alternative than to do the design first-time-right not to miss the window of opportunity. And that could be possible… Read More



Interface IP Protocols: Status
If your company develops Design IP to support well-known protocols like USB, PCIe, HDMI, DDRn memory controller, MIPI specification (and more), it’s crucial to know your competition, the market size by segment, and even more important the market potential by segment. The latest can be obtained by the Compound Annual Growth Rate… Read More
Taiwan Trip Report: The Coming Simulation Crisis!
Even though the flight to Taiwan is somewhat difficult, I really do enjoy my trips to Hsinchu. In addition to the top two pure-play foundries being there, one of the top SoC companies (MediaTek) and many of the leading semiconductor design companies are there as well. All are a quick taxi ride from my home away from home, the Hotel Royal.… Read More
Safer SoCs for safer driving
Flip on the TV, and a car commercial is bound to pop up shortly touting one of two technological aspects. One is center stack integration of smartphone-style applications. The other is advanced driver assistance systems (ADAS) featuring cameras, radar, and other sensors helping cars … Read More
Intel Core M vs Apple A8!
There were two big announcements last week right in my backyard and I missed them both! Instead, I was in Taiwan investigating yet another big development and all three of these events will intersect next year, absolutely.
At IDF in San Francisco Intel outlined the new 14nm Core M. This is an impressive CPU, one that will fill the now… Read More
Pole Pole All the Way to the Top
We made it! I have stood on the highest point in Africa, Uhuru Peak of Kilimanjaro.
Obviously this blog entry is totally off-topic. If you want to read about semiconductors and stuff, you can skip it.
So how do you get to the top of a nearly 20,000’ mountain? Slowly.
Slowly on two different levels. The first level is giving your body time… Read More
Sidense overlays OTP on TSMC 16nm FinFET
Process shrinks, which have served us well for most of the Moore’s Law journey, are reaching their limits. For switching transistors, the biggest problems of leakage current and gate oxide vulnerability in planar MOSFETs have led the industry to new 3D microstructures such as FinFET. For non-volatile memory, the problem is generally… Read More
Expert Tool to View and Debug Design Issues at Spice Level
Spice view of a design, block or fragment of the design is probably the lowest level of functional description of a circuit in terms of transistors, resistors, capacitors, interconnect and so on, which in several ways acts as an ultimate proof of pudding for any semiconductor design before manufacturing. However, it’s generally… Read More
Transceiver Verification of a 20nm Altera FPGA Device
FPGA devices are a great way to drive silicon technology development because they contain both digital and analog IP, along with sophisticated IO cells. The highest performance IOs are transceivers, and Altera has recently designed the Arria 10 device family to include up to 96 transceivers, using a 20nm technology that can achieve… Read More
Humans Need Not Apply!
With four children entering the job market I have a very simple piece of advice: DO NOT RUN FROM TECHNOLOGY, EMBRACE IT! Smartphones are now a “natural” part of modern life. We work on them, we play on them, we shop with them, we socialize with them, even risk our lives using them. Come on, every single person with a smartphone has used… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot