Architecture Exploration of Processors and SoC to trade off power and performance 5

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                    [post_content] => One of the challenges of designing a modern SoC is that the digital  parts of the circuit are really something that in an ideal world you'd  keep as far away from the analog as possible. The digital parts of the  circuit generate large amounts of noise, especially in the power supply  and in the substrate, two areas where it is impossible to completely  keep the analog and digital apart. Ideally, from a noise point of view,  we'd continue to put the digital and analog on separate chips (so no  shared substrate and minimal power supply coupling) but from a cost  point of view we have to put them on the same chip and analyze the  consequences.

 The existing static approaches to this problem, modelling the problem as IR drop in the power supply, have run out of steam for these SoCs with layers of power reduction techniques, and are lacking in both accuracy and capacity for analyzing the effects of transient power supply noise. Trying to do dynamic analysis using SPICE simulators runs into capacity limitations and using a simplified netlist reduces accuracy unacceptably. Substrate noise injection is a chip-wide phenomenon. Getting the analysis wrong can lead to expensive re-spins.

The shift to consumer, and especially to mobile applications, has meant that modern SoCs are designed with low-power taken into consideration from the start, with multiple power islands at different voltages. This makes the verification off transient noise even trickier, especially through the substrate.

Power gating, whereby blocks are completely powered down for extended periods, also makes verification more complex still due to the in-rush current when a block is turned back on. Turning on and off power domains needs to be modeled no just at the die level but also taking into account the package. Low ambient but high transient current, which results from this type of architectural approach is almost a worst case.

A simulation-based approach with large capacity and intelligent modeling is required to verify the power supply noise on this type of SoC. The validation methodology must verify power grid connection issues, investigate voltage sag, identify noise coupling between the various power domains and isolate EM b bottlenecks. The entire substrate must be modeled to see the impact of noise on victim circuits, especially an analog. What is required is nothing less than full Spice accuracy and full-chip capacity for transitent power-ground and EM analysis., along with modeling capabilities for system-level analysis.

 Read Arvind Shanmugavel's full full blog entry here.
Totem white papers is here.
The Apache webinar on mixed-signal power noise analysis is here.





 [post_title] => Noise Coupling [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => noise-coupling [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:44 [post_modified_gmt] => 2019-06-15 01:53:44 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/noise-coupling.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 828 [post_author] => 28 [post_date] => 2011-10-23 15:00:00 [post_date_gmt] => 2011-10-23 15:00:00 [post_content] => The TSMC OIP conference was Monday and Tuesday of last week. You have probably NOT read about it since it was invitation only and press was not invited. Slides were not made available (except for Mentor), no photos or video were allowed, it was a very private affair. Given that, I won’t be able to go into great detail but I will give you the impression it left on me and I will share slides from the best vendor presentation given on the second day.

TSMC OIP day 1 was for ecosystem partners (EDA, IP, Design Services) and I would say there were about 200 of us. My badge was courtesy ofSolido Design (I do the foundry work for Solido). Presentations were made by Cliff Hou, Vice President of Design Enablement, and LC Lou, Senior Director of IP Development and a couple of other TSMC guys that I did not know. I have worked with both Cliff and LC over the years and have a great respect and trust for them.

28nm and 20nm were discussed in great detail in regards to design enablement and IP. It was very clear that TSMC is finished with 28nm which ramped 3 times faster than 40nm. All 28nm process nodes: 28HP, 28HPL, 28LP and 28HPM (M=mobile) are in production with thousands of wafers already shipped to customers. This tracks with what I have heard from TSMC’s top customers, 28nm silicon is out and working. The first 20nm production wafers are scheduled for mid 2012. This also tracks with what customers have told me, who are finishing up 20nm PDKS in time for Christmas.

The technical deep dive was on RDRs (restricted design rules) which are new in 28nm. TSMC said it took customers about a month to adjust to RDRs which may be a little optimistic. The 28nm DRM (design rule manual) is significantly larger than 40nm, meaning the rules are more difficult to describe. Feedback I got from customers however was that RDRs made their life easier and without RDRs 28nm would not have yielded well at all.

3D IC was discussed in great detail which is a blog in itself. The takeaway here is that TSMC is leading the way in 3D IC, believe it. The other interesting topic was LDEs (layout dependent effects). New effects are coming at 20nm so you can bet LDE will be a big part of the next round of TSMC reference flows (13.0) you will see at the 2012 Design Automation Conference in San Francisco. These reference flows will probably be at 20nm since DAC is mid 2012, same as TSMC 20nm availability. Early access to process technology by both partners and customers was mentioned throughout the two days and I can tell you TSMC is doing much better with early access than other foundries, which was a clear differentiator for the top fabless companies at 28nm.

Day 2 was for customers which I would guess was close to a thousand people. Rick Cassidy, President of TSMC North America, did the keynote. Side note: Rick is a West Point graduate which may explain his no nonsense speaking style. Shang-Yi was next then Cliff Hou. The hot topic here was FinFets. I have blogged about this before but the message that day was FinFets would have delayed 20nm so TSMC stuck with planar transistors. The FinFet design ecosystem challenge was discussed (3D extraxtion, modeling, etc…) and TSMC flat out asked customers if they wanted FinFets for 14nm (2015). The customers I talked to will look at the technical versus time-to-market trade-offs of FinFets which is still being calculated.

Vendor presentations were next from Mike Inglis (ARM), Aart de Geus (Synopsys), Lip-bu Tan (Cadence), and Wally Rhines (Mentor). Mentor was the only vendor “open enough” to send me slides so that is the only presentation I will mention. According to Wally 28/20nm will be a “Golden Era” for foundries. Massive capital investment by foundries will yield (pun intended) very cost effective wafers that will absorb existing products at the higher nodes. 28/20nm cost and capability will also drive new applications and accelerate semiconductor industry growth for years to come. Absolfreakinlutely!




Wally’s presentation has 45 slides and several important points which should be independent blogs. His last slide is my favorite however, it is his personal collaboration ecosystem. My personal collaboration ecosystem is much larger of course since it includes all of you.
 [post_title] => TSMC 2011 Open Innovation Platform Ecosystem Forum Trip Report [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => tsmc-2011-open-innovation-platform-ecosystem-forum-trip-report [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:57 [post_modified_gmt] => 2019-06-15 02:40:57 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/tsmc-2011-open-innovation-platform-ecosystem-forum-trip-report.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 826 [post_author] => 20367 [post_date] => 2011-10-21 08:15:00 [post_date_gmt] => 2011-10-21 08:15:00 [post_content] =>  It is hard not to be impressed by Intel’s stunning financial performance since the 2008 downturn. They are on track to post revenue of $55B this year or 50% higher than 2008 while nVidia and AMD will be flat to less than 10% better. More significantly, earnings will be 3X that of 2008. More significantly, in the past 12 months they have funded a $10.5B CapEx budget, bought back $10B in stock and distributed roughly $4B in dividends. As for the stock: it is right around where it was September 1, 2008.

ARM continues to get the glory in the processor world at the expense of all other semiconductor vendors. Their P/E levitates at 69, a place that Intel occupied in the summer of 2000. I worked at Intel in the early 1990s and competed against them off and on with Cyrix and Transmeta until 2002. They are not only a tough competitor; they always have a backup plan that relies on another crank of the process technology to get them out of jams. Moore’s Law is devastating to upstarts and Intel is about to turn the crank one more time with 22nm. I listened to the earnings conference call 3 times with Paul Otellini and Company. It is amazing how matter of fact confident they are with their current execution and with what is coming down the pike.

Here are the facts that I found to be counter to the current thinking on Wall St. First, client computing is up 20%+ year-to-year. Data Center is up only 15%, but a new processor, Romley, looks to kick in soon. ASPs in the client space are flat and this is huge. It means that the integrated graphics is allowing Intel to hold up ASPs while at the same time minimizing the revenue of competitors (i.e. AMD and nVidia).

With regards to the coming Windows 8 O/S release, Otellini clearly communicated the strategy as it rolls out in consumer and enterprise. For consumer, Intel is willing to drop CPU+Graphics and Chipset down to $30 vs. $20 for AMD, a price premium the market is currently willing to pay. It is hard to see how ARM processors would get more than AMD’s price. Furthermore, Intel is funding the ultrabook effort that I am sure will result in some exclusivity over the next year or so.

As panels and other components drop in price, Intel will grow its percentage of the system BOM, something that today is occurring big time in the notebook market. In addition, from the sounds of the call, I am guessing Intel will ramp their NAND joint venture with Micron and begin to build SSDs, which implement a proprietary bus between the x86 mobile processor and the ultrabook fitted drives. Some ultrabook vendors are looking at a combo SSD and HDD to try to win customers over Apple MAC Air due to greater capacity. The SSD would contain the Windows O/S in order to provide faster O/S and Office boot and run time performance. As I read it, Intel says Ultrabooks are $899 this year, $699 next Q4 and with a 22nm Celeron in 2013 they drop into the $500s.

In the enterprise market, Intel said that corporations are only 50% of the way through their WinXP to Windows 7 upgrades cycle and it looks like there is another 18 months to go with this. In essence, Otellini is saying Intel’s client business has clear sailing through 2012 and into 2013. Although Windows 8 comes out in 2012, the SP1 (Service Pack 1) will not be available until sometime in 1H 2013. Historically, corporations hold off on PC upgrade cycles until SP1 is released. By then Intel’s complete line of 22nm Ivy Bridge processors will be deployed. Look for Intel to leverage the McAfee DeepSafe Security technology to keep corporations on board with Intel x86.

Finally, Otellini got around to addressing the competitive threat of ARM in a way that I thought should have been handled at a much earlier time frame (say 24 months ago). The assumption across the broad analyst community was that ARMs low power was inherently a function of architecture. My experience at Transmeta was eye opening in that when you dig down into the details of power and performance, you find that every workload has an optimum processor architecture. ARM has come from the bottom up and seeks to implement a Clayton Christensen version of Innovators Dilemma. If they were to have access to Intel’s Process Technology at the same time as Intel, then their momentum and the desire of customers to be free of Intel could be overwhelming. As Otellini stated, the competition with ARM comes down to Physics and not architecture. When you have equal workloads, then the winning processor is the one that gets the work done with the best transistors. Intel wins on transistors.

Otellini has crafted an internal business model that is becoming more leveraged on the value of process technology and the lead Intel enjoys over TSMC and other Foundries. As a baseline it appears that Intel will continue to serve the client market with x86 processors (including chipsets) with 50%+ gross margins. For enterprise it is 60%+ and for Xeon based servers it is 80%+. The alternative business model that is waiting in the wings is the Leading Edge Foundry model that Apple is best primed to take advantage of. If Apple utilizes 22nm at Intel while they are simultaneously at 28nm with TSMC, then Apple will pay Intel a 60%+ gross margin for the benefit of a 50% die size and power reduction.

There is one more alternative path to the above model that is even more attractive to Intel and Apple. Apple agrees to prepay Intel for a fab expansion outside the US in return for parts with lower ASPs. The reason it is outside the US is because that is where Apple has most of its $81B in cash to avoid US taxes on repatriation. Imagine the competitiveness of an Intel 22nm fab partially funded by Apple based in Israel vs. a TSMC 28nm Fab based in Taiwan.




Full Disclosure: I own Intel and Apple Stock

 [post_title] => Intel’s Incredible Semiconductor Machine [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => intels-incredible-semiconductor-machine [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:55 [post_modified_gmt] => 2019-06-15 02:40:55 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/intels-incredible-semiconductor-machine.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 684 [post_author] => 3 [post_date] => 2011-10-20 09:56:00 [post_date_gmt] => 2011-10-20 09:56:00 [post_content] => I've blogged about the Calibre family of IC design tools before:


Smart Fill replaced Dummy Fill Approach in a DFM Flow


DRC Wiki


Graphical DRC vs Text-based DRC


Getting Real time Calibre DRC Results with Custom IC Editing


Transistor-level Electrical Rule Checking


Who Needs a 3D Field Solver for IC Design?


Prevention is Better than Cure: DRC/DFM Inside of P&R


Getting to the 32nm/28nm Common Platform node with Mentor IC Tools


If you want some hands-on time with the Calibre tools then consider attending the October 27th workshop in Fremont, California.


[post_title] => Oct 27 - Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California) [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => oct-27-hands-on-workshop-with-calibre-drc-lvs-dfm-xrc-erc-fremont-california [to_ping] => [pinged] => [post_modified] => 2011-10-20 09:56:00 [post_modified_gmt] => 2011-10-20 09:56:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/oct-27-hands-on-workshop-with-calibre-drc-lvs-dfm-xrc-erc-fremont-california.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 824 [post_author] => 3 [post_date] => 2011-10-19 15:40:00 [post_date_gmt] => 2011-10-19 15:40:00 [post_content] =>  AnSem has been in the AMS design business since 1998 and uses a variety of commercial EDA tools along with internally developed tools and scripts to automate the process of analog design and technology porting. Their IC designers have completed some 40 AMS projects in diverse areas like:

  • RF CMOS

    • LNA, VCO, Mixers
    • Synthesizers
    • Low-IF/Zero-IF


  • Low Power / Low Voltage

    • 1v wireless TRx
    • Power management
    • Battery operation


  • Data Acquisition

    • Sensor interfacing
    • A/D
    • D/A


  • High Speed Data Communication

    • SerDes
    • Line driver/Receiver
    • PLL, CDR




Commercial EDA Tools

Best in class is the tool selection methodology used at AnSem, with the following EDA tools used for specification, design, optimization and verification:

High level modeling and verification - Matlab Simulink

Top down modeling, bottom up design - VHDL-AMS using Mentor's Questa ADMS (Eldo, Eldo RF, ADiT). This can be used for models of a receiver, demodulation and PLL circuits.

Digital Simulation - Mentor's Questa (ModelSim)

Transistor layout and sizing - Internal tools, Tanner EDA (L-Edit, HiPer Layout)

IC Layout - Cadence Virtuoso

Internal EDA Tools
One of the internally developed tools is called AnSem Advanced Proprietary Synthesis Tool (APST) and it fits into the design flow to develop analog cells for the purpose of design re-use and technology porting. Building IP that can be re-used at new nodes is achievable with APST. The transistor sizing done by APST is used in the Tanner EDA tools.

PLL designs are optimized with a tool called PLLOP. RX noise gain and blocking analysis is performed by a tool called MREX. Finally, there are application-specific Matlab toolboxes created to automate tasks like FSK demodulation.

Automated IP
AnSem engineers have created many IP blocks with an automated design approach:

  • VCO with on-chip integrated inductors
  • LNA with on-chip inductors
  • Delta-Sigma A/D: switched-cap
  • Comparator: High Speed, Flash
  • OTAs and OpAmps for low-frequeny
  • OTA-C filters for active-RC type circuits
  • Bandgap reference circuits

Experience with Tanner EDA Tools

AnSem first started using the Tanner EDA tools right from the start in 1998 because they could design their IP blocks and use the tools at a reasonable cost. Today the designs can target even the 40nm node and the design complexity has increased significantly.

Using schematics and layout from Tanner in Cadence Virtuoso is now possible with the Open Access (OA) database. Interoperability is an important trend for EDA tools and has provided AnSem some flexibility. Customers of AnSem user different IC tools so working with industry standards like OA meets the need.

Learning the Tanner tools was intuitive as they are based on the popular Windows operating system and GUI. Designers can extend the features of the tools by scripting, all without having a specialized CAD department.

DRC and LVS are done with Tanner and the rules from Mentor's Calibre tool are imported.

Conclusion
AnSem has assembled both commercial and internal EDA tools to automate their AMS design for both ASIC and custom IC design work. Customers of AnSem include: Tyco Electronics, Oce Technologies, Phonak, Cochlear, Kawasaki Microelectronics, National Semiconductor and NXP.


[post_title] => AMS Design at AnSem [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => ams-design-at-ansem [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:42 [post_modified_gmt] => 2019-06-15 01:53:42 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/ams-design-at-ansem.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 823 [post_author] => 9491 [post_date] => 2011-10-19 14:01:00 [post_date_gmt] => 2011-10-19 14:01:00 [post_content] =>  There are lots of places that Apache is going to popping up in the next few weeks.

Firstly, Andrew Yang will deliver the keynote on October 24th at the Electrical Performance of Electronic Packaging and Systems (EPEPS) in San Jose. He will be talking about "Chip-Package-System convergence: bridging multiple disciplings to solve low power, cost down and system reliability challenges."

And the following day at EPEPS, Dr Dian Yang (TIL there are two Dr Yangs at Apache) is on a panel session about the main challenges of high-speed packaging and interconnect.

You can register for EPEPS here.

 If EPEPS isn't your thing, then how about the ARM Techcon 2011. It takes place from 25-27th October in the Santa Clara convention center. The 25th is chip design day (the other two days are dedicated to system and software) and Apache will be participating.

And if Santa Clara is not your thing, ARM Techcon is in Hsinchu on November 18th and in Paris on December 8th.


 Next up is MEPTEC (Microelectronics Packaging and Test Engineering Council) conference on "2.5D, 3D and beyond" on November 9th in Santa Clara. I'm looking for the low-down on packaging in the fourth dimension! Aveek Sarkar will be presenting on "Thermal power distribution and reliability interactions in 2.5/3D packaging-modeling."


 And finally, for today, if you are in China in December, the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) is taking place December 12-14th in Hangzho. Apache will be presenting. More details later. [post_title] => Apache on the Road [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => apache-on-the-road [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:41 [post_modified_gmt] => 2019-06-15 01:53:41 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/apache-on-the-road.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 822 [post_author] => 12 [post_date] => 2011-10-19 10:26:00 [post_date_gmt] => 2011-10-19 10:26:00 [post_content] => SICAS (Semiconductor Industry Capacity Statistics) has released its 2Q 2011 data with significant changes in membership. The data is available through the SIA at: SICASdata The SICAS membership list no longer includes the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) or United Microelectronics Corporation (UMC). These companies had been in previous SICAS data for several years. Nanya is a relatively small semiconductor manufacturer with revenue of $1.8 billion in 2010. TSMC and UMC are the two largest semiconductor foundries, with 2010 revenues of $13.3 billion and $4.0 billion, respectively. IC Insights, which includes foundries in its rankings of semiconductor suppliers, listed TSMC as the third largest semiconductor supplier in both 2010 and 1[SUP]st[/SUP] half 2011. UMC was 19[SUP]th[/SUP] in both rankings. ICInsights Rankings

The only other change in SICAS participants is the omission of National Semiconductor. The National data may be included with Texas Instruments, which acquired National effective September 27, or may have been neglected during the transition. National’s revenue for its fiscal year ended May 2011 was $1.5 billion.

We at Semiconductor Intelligence estimate TSMC and UMC represented about 16% of total IC capacity in SICAS. Thus losing these companies has caused a major disruption in SICAS data and makes comparison ofthe 2Q 2011 data with previous quarters invalid in most categories. However TSMC and UMC release information on wafer capacity and shipments in their quarterly financial releases. Thus adding the reported TSMC and UMC 2Q 2011 data to the SICAS data results in total IC data which is more comparable to prior quarters.

The chart below shows SICAS data for total IC capacity in thousands of eight-inch equivalent wafers per week. Capacity for TSMC and UMC was added to the SICAS 2Q 2011 capacity for comparison with prior quarters. 2Q 2011 IC capacity (including TSMC and UMC) was 2,084 thousand wafers, up 1.6% from 2,052 thousand in 1Q 2011 and the fifth consecutive quarterly increase. IC capacity in 2Q 2011 was still 6% below the record capacity of 2,223 thousand wafers in 3Q 2008. The adjusted 2Q 2011 data is still not entirely comparable to prior SICAS data since Nanya (and possibly National) are no longer participating.



The March 11, 2011 Japanese earthquake and tsunami also had some impact on capacity. The disaster affected several wafer fabs either through direct damage or through power outages. Since SICAS data is based on average capacity throughout a quarter, the impact on 1Q 2011 SICAS data was not likely significant. Most of the affected fabs were back to full production by the end of April. Almost all of the fabs were back up by mid July. Although the size of the impact is difficult to estimate, 2Q 2011 capacity and utilization would have been somewhat higher if not for the Japan disasters.

SICAS reported total IC capacity utilization of 92.2% in 2Q 2011, down 2.0 percentage points from 94.2% in 1Q 2011. The change in participants makes the 2Q 2011 SICAS data not directly comparable to 1Q 2001. Adding capacity and shipment data for TSMC and UMC in 2Q 2011 enables a more apples-to-apples comparison. In this second case, total IC capacity utilization was 92.8% in 2Q 2011, down 1.4 points from 1Q 2011. Another way to make a more equivalent comparison is to use SICAS data for MOS IC capacity without foundry wafers. This category was not as affected by the participant changes since TSMC and UMC reported in the foundry category. Utilization for MOS ICs without foundry was 92.4% in 2Q 2011, down 1.2 points from 93.6% in 1Q 2011.



Thus industry total IC capacity utilization dropped in 2Q 2011 from 1Q 2011, but not by the 2 points indicated by the SICAS data. If the same participants were in both 1Q and 2Q data, the utilization drop probably would have dropped by about 1.2 to 1.4 points. IC capacity utilization has been above 90% for six consecutive quarters following the 2008-2009 downturn.

The change in participants in SICAS is disappointing. SICAS has enjoyed fairly high participation rates since it was formed in 1995. As a member of the SICAS founding executive committee I remember the spirit of cooperation as foundry companies and integrated device manufacturers were willing to share data for the first time, with the goal of providing useful information for the entire semiconductor industry.





 [post_title] => SICAS capacity data loses TSMC and UMC [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => sicas-capacity-data-loses-tsmc-and-umc [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:54 [post_modified_gmt] => 2019-06-15 02:40:54 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/sicas-capacity-data-loses-tsmc-and-umc.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 818 [post_author] => 20367 [post_date] => 2011-10-18 17:00:00 [post_date_gmt] => 2011-10-18 17:00:00 [post_content] =>  Vertical integration, as I have noted in previous blogs, is the way to domination and maximum profitability. That is unless someone else has beaten you to the punch with an even bettermodel. Apple is now executing a product and manufacturing supplier strategy that will force Samsung to lose lots of money and then ultimately split the Semiconductor Group from the larger Samsung Corporate Umbrella. Apple owns the Commanding Heights of the new Computer Ecosystem and has mapped out the more profitable Virtual Vertical Manufacturing Structure that allows it to invest just a portion of the CapEx that traditional suppliers require. Hence, they are growing in profitability at a greater rate than traditional vertically integrated companies. Samsung will need to split off its Semiconductor Unit soon or they will face even greater losses because they will be put in an untenable situation by Apple’s soon to be executed actions.

Most of my recent blog posts have been focused on Apple for one reason. They are re-writing the book on how to run a superior company, from products to manufacturing, and this is having a dramatic impact in the semiconductor industry playing field. Many people focus on the products – which are outstanding. But the other side of the house is cranking on a model that will dramatically increase profit margins at the expense of a multi-sourced supplier base that will ultimately succumb to their wishes (any of their wishes). The readers must understand that Apple can punish as well as incentivize suppliers at their choosing. As I outlined in a blog a few weeks ago Apple is the “swing consumer” of the semiconductor industry (see Apple Plays Saudi Arabia’s Role in the Semiconductor Market). Therefore, they dictate market pricing for many components.

As many of our readers are aware, Apple started a legal process several months ago to keep Samsung Tablets out of worldwide markets because the product looked similar to the iPAD. Samsung is the only company in the world that can challenge Apple on a vertical cost basis and they have the added advantage of having corporate subsidies. Apple’s goal in the coming year is to make Samsung retreat from the consumer market and back into semiconductors or risk losing an excessive amount of money.

The Global Semiconductor market is going through some softness as of late. However, DRAM is very sick and NAND is doing just OK - overall. The picture, I contend, is different if we look vendor by vendor. In a downturn, the largest semiconductor vendor with the biggest CapeEx gets hit worse than the smallest guy. So Samsung is now feeling maximum pain.

Recently, Apple let it be known that it was shifting DRAM and NAND out of Samsung to Toshiba and Elpida. Here’s where it gets interesting. Apple, as recently discussed, has over 70% gross margins in its iPhone 4S so they can afford to pay a little more to certain suppliers that they seek to gain favor with at the expense of a “Bad Supplier.” I contend that Apple is probably paying higher ASPs to Toshiba and Elpida in the short run to get more of their capacity and to penalize Samsung. Samsung is now looking at reduced demand and the prospect of selling out DRAM and NAND at a lower ASP to the gray market. Remember in down times, gray markets have ASPs substantially below contract price. A lot of bleeding is going on. (see Samsung Sees Weaker Earnings)

From a long-term point of view, it is difficult for Samsung to plan for new fabs if they don’t know how much demand they can expect from Apple. And now, Apple is raising the competitive profile of Toshiba and Elpida at Samsung’s expense. If Samsung gets out of the Tablet and Phone market, then that will free Apple to expand into the 25% of the market (phones) that will be like green fields with 70%+ gross margins. And all this occurs by just paying Toshiba and Elpida a few extra cents per part.

Splittsville Time is Approaching.




 [post_title] => Apple is Giving Samsung Semiconductor A Splitting Headache [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => apple-is-giving-samsung-semiconductor-a-splitting-headache [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:52 [post_modified_gmt] => 2019-06-15 02:40:52 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/apple-is-giving-samsung-semiconductor-a-splitting-headache.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 817 [post_author] => 4 [post_date] => 2011-10-18 06:38:00 [post_date_gmt] => 2011-10-18 06:38:00 [post_content] => Very interesting question from Zahrein in this thread: “how to manage an embedded USB 3.0 PHY Verification”? To clearly position the problem, Zahrein need to run the RTL verification of a complete SoC integrating an USB 3.0 function, that is the Controller (digital) and the PHY (Analog Mixed Signal) embedded in the SoC. The question, as asked by Zahrein, is “inside the USB3 block, we will have a lot of Mixed signals and hence the AMS verification is needed but as a USB3 block connect to the core or IP's, do we need AMS verification. I believe the Full chip RTL validation would cover it as the Data_In and Data_out is in digital waveform”.

In fact the answer is “No”, you don’t need to run AMS verification at this stage (RTL of the complete SoC), but, immediately comes a condition: as far as the PHY-specific Mixed Signal verification has been done already, and this should be part of the PHY development methodology. The next question quickly comes: is the PHY developed internally, or has it been sourced from an IP vendor? If the latest is true, the solution is not far away.

According with Navraj Nandra, Director for AMS IP at Synopsys: “after integration of the PHY into the ASIC, USB3.0 functional (logical) verification must be done at a “system level” including at a minimum, the PHY, the link-layer controller (host/device, etc.), and any VIPs. For functional verification, Synopsys ships a verilog simulation model in which the digital-logic portion of the PHY is represented by flattened GTECH netlists, and the analog portions of the PHY are represented by behavioral verilog. This verilog model can then be dropped into a simulation bench in which the other elements (e.g. link-layer controller, VIPs, etc..) are instantiated, and functional scenarios can be simulated.”



In other word, the customer doesn’t need to run AMS verification, the PHY is represented by behavioral Verilog model, and you can run a complete “digital-only” verification.

Now, if the PHY has been internally developed, the above methodology can be applied, at the condition that the PHY development team has run PHY-specific Mixed Signal verification, and generated RTL simulation model (digital-logic portion of the PHY represented by flattened netlists, and the analog portions of the PHY are represented by behavioral RTL).

In the “make versus buy” problematic, it shows that the internal PHY development team should behave exactly as an IP vendor, offering the same level of service. As a side remark (here I remember the time where I was doing SoC integration, including AMS and digital functions being provided by different design team within the company) such a “service” can be more difficult to obtain when you are an internal customer than when you are paying a license fee to an IP vendor…


Let’s imagine now that we are doing engineering in the real life (the place governed by the laws of Physics, as well as Murphy’s laws). The above described methodology has been deployed, you have run RTL simulation, and you feel that a scenario is not working quite as expected, and narrows it down to the PHY level. If the PHY has been sourced to Synopsys, Navraj’s suggestion is that the customer:

(a) captures VCD waveforms for this scenario just at the top-level of the PHY,
(b) Open a Synopsys Solvnet case for this, and upload the waveforms on the Solvnet case.


As part of Synopsys customer support, they’ll review it and determine what the problem is.


If the PHY has been internally sourced, there is certainly a similar solution, involving the PHY development team and AMS verification, but the important point here is that the SoC integrator doing RTL verification at the chip level (or below) should not be involved in AMS-level verification.

Hope this answer to Zahrein’s question…

Any comment from the design community is welcomed, as well as mentioning any other approach working for such a scenario!

Eric Esteve from IPNEST – Table of Content for “USB 3.0 IP Forecast 2011-2015” available here




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Tomorrow in San Jose
you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.



Here are some of the topics that will interest IC designers using Mentor tools:

iLVS: Accessible, Supportable Paradigm for Circuit Verification at Advanced Nodes (2:30PM, EDA Track)
Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. The number of layers and layer derivations are increasing and the complexity of devices, especially Layout Dependent Effects (LDS), becomes harder and harder to model. In the past, customers could take a foundry rule deck and easily modify it to include their own device models for transistors, resistor, capacitors, inductors, etc., and even augment the deck with their own checks. At 40nm, 28nm, few customers are able to do this confidently. To address this situation, TSMC and Mentor Graphics will discuss how they collaborated to define iLVS, a syntax that provides customers with a more easily adaptable solution to their circuit verification needs. Using iLVS, users can more easily modify and augment foundry rule decks, yet still adhere to the modeling and manufacturing intent captured in these decks.


Keys to Successful DFM Partnership (4:00PM,IP/EDA/Services Track)
DFM is now a known necessity for advanced nodes. But a successful DFM strategy is more than a “push button” solution. It depends on a synergistic combination of tool technology and design methodology, and close collaboration with the foundry. In this session, CSR and Mentor will relate their personal experiences with DFM, its implementation in the TSMC ecosystem, discuss critical factors that determine the difference between success and failure in actual practice.


Challenges and Directions for Next Generation 3D-IC (4:30PM, EDA Track)
The IC industry is steadily moving to the third dimension of scaling, i.e., stacking die vertically using through silicon vias (TSVs) to make inter-die connections in a manner analogous to copper vias in multi-layer printed circuit boards (PCBs), but on a much smaller scale. The 2.5D interposer solution is here today, but next generation, ergo full 3D, will bring additional complexities. For example, when TSVs are introduced into the active area of an IC, things get complicated due to complex electrical, mechanical stress and thermal interactions that impact circuit performance and reliability. In this session Qualcomm and Mentor Graphics will discuss some of the challenges of designing 3D-ICs and what the ecosystem is doing to provide the needed methods and tools to make next generation 3D-IC a reality.


Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes (5:00PM,IP/EDA/Services Track)
Preventing electrical circuit failure is a growing concern for IC designers today. For certain types of failures such as Electrostatic discharge (ESD) issues, there are well established best practices and design rules that circuit designers should be adhering to. Other issues are more recent, such as the best way to design circuits that cross different voltage regions on a chip. While these topics are not unique to a specific technology node, in particular for analog mixed signal they become increasingly critical as the oxides get thinner for the most advanced nodes and as circuit designers continue to put more and more voltage regions on-chip. To validate that circuits have robust protection from electrical failure, TSMC and MGC will present how they have partnered to define and develop rule decks that enable automatic advanced circuit verification to address these issues at the 28nm and 40nm nodes.


Information on the TSMC Open Innovation Platform Ecosystem Forum is here.


[post_title] => Mentor at the TSMC Open Innovation Platform Ecosystem Forum [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => mentor-at-the-tsmc-open-innovation-platform-ecosystem-forum [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:39 [post_modified_gmt] => 2019-06-15 01:53:39 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/mentor-at-the-tsmc-open-innovation-platform-ecosystem-forum.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 829 [post_author] => 9491 [post_date] => 2011-10-24 08:47:00 [post_date_gmt] => 2011-10-24 08:47:00 [post_content] => One of the challenges of designing a modern SoC is that the digital parts of the circuit are really something that in an ideal world you'd keep as far away from the analog as possible. The digital parts of the circuit generate large amounts of noise, especially in the power supply and in the substrate, two areas where it is impossible to completely keep the analog and digital apart. Ideally, from a noise point of view, we'd continue to put the digital and analog on separate chips (so no shared substrate and minimal power supply coupling) but from a cost point of view we have to put them on the same chip and analyze the consequences.

 The existing static approaches to this problem, modelling the problem as IR drop in the power supply, have run out of steam for these SoCs with layers of power reduction techniques, and are lacking in both accuracy and capacity for analyzing the effects of transient power supply noise. Trying to do dynamic analysis using SPICE simulators runs into capacity limitations and using a simplified netlist reduces accuracy unacceptably. Substrate noise injection is a chip-wide phenomenon. Getting the analysis wrong can lead to expensive re-spins.

The shift to consumer, and especially to mobile applications, has meant that modern SoCs are designed with low-power taken into consideration from the start, with multiple power islands at different voltages. This makes the verification off transient noise even trickier, especially through the substrate.

Power gating, whereby blocks are completely powered down for extended periods, also makes verification more complex still due to the in-rush current when a block is turned back on. Turning on and off power domains needs to be modeled no just at the die level but also taking into account the package. Low ambient but high transient current, which results from this type of architectural approach is almost a worst case.

A simulation-based approach with large capacity and intelligent modeling is required to verify the power supply noise on this type of SoC. The validation methodology must verify power grid connection issues, investigate voltage sag, identify noise coupling between the various power domains and isolate EM b bottlenecks. The entire substrate must be modeled to see the impact of noise on victim circuits, especially an analog. What is required is nothing less than full Spice accuracy and full-chip capacity for transitent power-ground and EM analysis., along with modeling capabilities for system-level analysis.

 Read Arvind Shanmugavel's full full blog entry here.
Totem white papers is here.
The Apache webinar on mixed-signal power noise analysis is here.





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Noise Coupling

Noise Coupling
by Paul McLellan on 10-24-2011 at 8:47 am

One of the challenges of designing a modern SoC is that the digital parts of the circuit are really something that in an ideal world you’d keep as far away from the analog as possible. The digital parts of the circuit generate large amounts of noise, especially in the power supply and in the substrate, two areas where it is impossible… Read More


TSMC 2011 Open Innovation Platform Ecosystem Forum Trip Report

TSMC 2011 Open Innovation Platform Ecosystem Forum Trip Report
by Daniel Nenni on 10-23-2011 at 3:00 pm

The TSMC OIP conference was Monday and Tuesday of last week. You have probably NOT read about it since it was invitation only and press was not invited. Slides were not made available (except for Mentor), no photos or video were allowed, it was a very private affair. Given that, I won’t be able to go into great detail but I will give you… Read More


Intel’s Incredible Semiconductor Machine

Intel’s Incredible Semiconductor Machine
by Ed McKernan on 10-21-2011 at 8:15 am

It is hard not to be impressed by Intel’s stunning financial performance since the 2008 downturn. They are on track to post revenue of $55B this year or 50% higher than 2008 while nVidia and AMD will be flat to less than 10% better. More significantly, earnings will be 3X that of 2008. More significantly, in the past 12 months they have… Read More


Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 10-20-2011 at 9:56 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow

DRC Wiki

Graphical DRC vs Text-based DRC

Getting Real time Calibre DRC Results with Custom IC Editing

Transistor-level Electrical Rule Checking

Who Needs a 3D Field Solver for IC Design?

Prevention is BetterRead More


AMS Design at AnSem

AMS Design at AnSem
by Daniel Payne on 10-19-2011 at 3:40 pm

AnSem has been in the AMS design business since 1998 and uses a variety of commercial EDA tools along with internally developed tools and scripts to automate the process of analog design and technology porting. Their IC designers have completed some 40 AMS projects in diverse areas like:

  • RF CMOS
    • LNA, VCO, Mixers
    • Synthesizers
    • Low-IF/Zero-IF
Read More

Apache on the Road

Apache on the Road
by Paul McLellan on 10-19-2011 at 2:01 pm

There are lots of places that Apache is going to popping up in the next few weeks.

Firstly, Andrew Yang will deliver the keynote on October 24th at the Electrical Performance of Electronic Packaging and Systems (EPEPS) in San Jose. He will be talking about “Chip-Package-System convergence: bridging multiple disciplings… Read More


SICAS capacity data loses TSMC and UMC

SICAS capacity data loses TSMC and UMC
by Bill Jewell on 10-19-2011 at 10:26 am

SICAS (Semiconductor Industry Capacity Statistics) has released its 2Q 2011 data with significant changes in membership. The data is available through the SIA at: SICASdata The SICAS membership list no longer includes the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) or UnitedRead More


Apple is Giving Samsung Semiconductor A Splitting Headache

Apple is Giving Samsung Semiconductor A Splitting Headache
by Ed McKernan on 10-18-2011 at 5:00 pm

Vertical integration, as I have noted in previous blogs, is the way to domination and maximum profitability. That is unless someone else has beaten you to the punch with an even bettermodel. Apple is now executing a product and manufacturing supplier strategy that will force Samsung to lose lots of money and then ultimately split… Read More


USB 3.0 PHY Verification: how to manage AMS IP verification?

USB 3.0 PHY Verification: how to manage AMS IP verification?
by Eric Esteve on 10-18-2011 at 6:38 am

Very interesting question from Zahrein in this thread: “how to manage an embedded USB 3.0 PHY Verification”? To clearly position the problem, Zahrein need to run the RTL verification of a complete SoC integrating an USB 3.0 function, that is the Controller (digital) and the PHY (Analog Mixed Signal) embedded in the SoC. The question,… Read More


Mentor at the TSMC Open Innovation Platform Ecosystem Forum

Mentor at the TSMC Open Innovation Platform Ecosystem Forum
by Daniel Payne on 10-17-2011 at 3:14 pm

EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.

Tomorrow in San Jose
you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.

Here are some of the topics that will interest IC designers… Read More