SIC 2020 Forum 800x100

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                    [post_date] => 2010-10-24 12:58:00
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                    [post_content] => First of all it was not a rant, it was a clearly scripted rebuttal to the competitive pressures Apple is feeling from Android (here). As I blogged before, Apple is the Open Standards Antichrist  and is trying to monopolize the trillion dollar mobile internet  ecosystem with a CLOSED platform. According to Steve Jobs, “Open systems  don’t always win.” Say what!?!?!?

At the heart of the issue is the mobile operating systems Apple iOS and Google Android, so lets not forget the operating system wars of the 1980’s and 1990’s. Berkley UNIX Versus System V, which is today LINUX, a truly open system supported by all. I’m not saying it’s going to be a smooth ride for Android 3.0 integrators but open operating systems will prevail, believe it. Mac OS versus Windows, right? Steve Jobs can rant all he wants but in the end it is our vote that counts, which is why I don’t own a Mac, iPhone or iPad. DOWN with tyrany! Vote for FREEDOM of choice! Vote for the GINGERBREAD man!

Coincidently, the Silicon Integration Initiative (Si2) Open Access Conference was last week to which I was cordially invited. I mention this not just because it included a free lunch (I blog for food), it is also something I feel is critical to the future of the semiconductor design ecosystem. Richard Goering already did a nice write-up (here) so I will skip right to the most critical Open Standards issue facing semiconductor design today, the Process Design Kit TUG OF WAR!

The PDK is the contract between fabless semiconductor companies and the foundries containing the secret sauce of semiconductor manufacturing. The information inside a PDK is worth billions of dollars so it is protected accordingly. Unfortunately EDA tools require this information as well so EDA companies are the cheese in this symbiotic grilled cheese sandwich. Since EDA companies work with all of the foundries the opportunity for secret sauce leaks is always there. Since EDA companies try to get their proprietary formats into PDKs to lock in customers there will never be peace and harmony within the OpenPDK or IPL initiatives.

In my humble but expert opinion PDKs should be treated like a platform with apps, not unlike the smartphone, tablet PC, and now big screen TVs. Unfortunately it will take a company with the market share of an Apple, Google, or Samsung to be successful with this type of platform/app strategy. Fortunately we have such a company in the semiconductor industry and that, of course, is TSMC.

The TSMC iPDK (interoperable process design kit) initiative was announced on 7/21/2009 for 65nm and below. By keeping EDA vendors on TOP of the platform, TSMC can guard the secret sauce while sharing it with early access (top tier) fabless semiconductor companies. By lowering the cost of design apps, emerging fabless semiconductor companies can flourish. By keeping proprietary EDA formats OUT of the iPDK, TSMC can give customers the FREEDOM of choice!

Of course this gives TSMC the opportunity to monopolize the market so the OpenPDK initiative must also adopt a platform strategy and serve as a counter balance to iPDK. Use the comment section to voice your opinion on this very sensitive but crucial topic. Semiconductor design ecosystem decision makers and influencers subscribe to my blog, absolutely. [post_title] => Steve Jobs’ 5 Minute Anti Open Systems Rant! [post_excerpt] => [post_status] => publish [comment_status] => closed [ping_status] => closed [post_password] => [post_name] => steve-jobs-5-minute-anti-open-systems-rant [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:37:26 [post_modified_gmt] => 2019-06-15 02:37:26 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/486-steve-jobs-5-minute-anti-open-systems-rant/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 439 [post_author] => 28 [post_date] => 2010-10-22 18:41:00 [post_date_gmt] => 2010-10-22 18:41:00 [post_content] =>
The semiconductor analysts are at it again, revising numbers, polishing their guesstimates, and patting each other on the back for being equally as inaccurate. I blame these crystal ball hacks for the semiconductor shortages and price hikes we are experiencing today.

These people get paid to guide investors, and the industry as a whole, to prevent chaos and catastrophe and they have failed us all. Last year semiconductor related manufacturing facilities went dark, people lost jobs, capacity expansion plans were put on hold. It will take years to recover the stability required for a healthy semiconductor growth cycle.

“All signs point to another semiconductor downturn as there have now been signs of softening demand from approximately 65 percent of total semiconductor demand,” wrote Christopher Danely, an analyst at J.P. Morgan, in a report circulated Wednesday (Aug. 18).

Danely also said semiconductor stocks peaked in 2Q10 and he expects utilization rates will peak in 3Q10.Why trust an analyst from a financial services firm that may or may not be short on semiconductor stocks? This is deja vu of my blog “Colossal Failure of Common Sense”, where these dirty scoundrels nearly bankrupted us, stealing our home equity, all while taking home million dollar bonuses, but I digress.

The most recent post by Bill Jewell at Semiconductor Intelligence suggests capacity utilization will continue to increase through the rest of the year, hitting 96 percent in the fourth quarter. I’m with Bill on this one. Capacity has still not rebounded from the 2009 fiasco but with the most recent semiconductor capital expenditures you can bet it will, with a vengeance:

[LIST=1]
  • Samsung $15.3B
  • TSMC $5.9B
  • Intel $3.6B
  • GFI $2.7B
  • Toshiba $2.1B
  • Hynix $2.1B
  • UMC $1.8B
  • Inotera $1.5B
  • Nanya $1.4B
  • Elpida $1.0B

    As compared to numbers reported by iSupply earlier this year:

    The capacity numbers that interest me the most are the 300mm fabs at 65nm and below, that is where the billions of dollars of capital expenditures are going. 300mm manufacturing technology is where the smartphone and other key enabling semiconductor technology comes from. At 300mm, UMC and TSMC are both running at 100% and will continue to do so for the next year or two as these are the same fabs that produce 40nm and 28nm. Both UMC and TSMC have increased 300mm production this year due to efficiencies and existing expansion projects. TSMC will also complete their 3rd GigaFab (FAB 15) next year. Global Foundries 300mm Fabs (1,7,8) will see increases this year of 20%. With additional expansions and the new 300mm fab in New York, GFI should break 2M 300mm wafers per year by 2015.


    The questions I have are:

    [LIST=1]
  • Will the semiconductor industry continue to grow at single or double digits?
  • Are the foundries overspending on capacity?
  • Will there be a slingshot effect with overcapacity starting in 2012?

    Rather than ask the so called experts I would rather hear it from the people who actually design and manufacture semiconductors. When I Google search, I always read the Wikipedia entry first, trusting the collective wisdom of millions versus a biased person who stole my home equity.


    lang: en_US

    [post_title] => Semiconductor Supply and Demand in 2010/2011 [post_excerpt] => [post_status] => publish [comment_status] => closed [ping_status] => closed [post_password] => [post_name] => semiconductor-supply-and-demand-in-2010-2011 [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:37:26 [post_modified_gmt] => 2019-06-15 02:37:26 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/semiconductor-supply-and-demand-in-2010-2011.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 239 [post_author] => 18791 [post_date] => 2010-10-21 07:28:00 [post_date_gmt] => 2010-10-21 07:28:00 [post_content] => A venture capitalist offered the advice, "Startup investors are attracted by good people making a good product for a growing market." That wisdom, as much as any served as the foundation for the company Mentor Graphics would become.
     Founders outside of G-7. Clockwise from top left: Charlie Sorgie, Dave Moffenbeier, Steve Swerling,Tom Bruggere, Jack Bennett Seated from left: Gerry Langeler, Rick Samco, Ken Willett, John Stedman

    How it Started - Capital Ideas


    The founding engineers, whose backgrounds were in software development, ruled out designing and manufacturing proprietary computers to run their software applications because they felt that hardware was going to become a commodity owned by big computer companies. Instead they would select an existing computer system as the hardware platform for the CAE programs they would build.

    The business plan presented to the financiers revealed that the team had found a market of rich potential and all the other necessary ingredients for success. "The Computer Aided Engineering (CAE) business is a superset of the CAD/CAM industry," the document began. "We can define computer aided engineering products as equipment and software which enable an engineer to improve … productivity, work quality and consistency." The plan noted "rapid growth" in CAD/CAM "and to an even greater degree in the emerging special purpose workstation environment." Driving forces in the field were identified as "a shortage of both engineers and trained technicians, and the push for productivity and quality in basic manufacturing industries."

    The first round of money, $1 million, came from three of the most prestigious venture capital firms in the country: Sutter Hill of Palo Alto, Greylock of Boston and Venrock Associates of New York. These firms had financed such giants of high technology as Apple and Intel. The combined power of their participation produced another $2 million from Hambrecht & Quist, L.F. Rothschild, Unterberg and Towbin, and Lamereaux and Glynn by the summer of 1982. In April 1983, the original investors and nine new ones put another $7 million into Mentor Graphics. Thus, Mentor Graphics became the first company to attract world-class venture capital to Oregon.


    The Hardware Choice


    Choosing the best hardware on which to base the software was the next big step to take. While there were a range of options available, from Apple to "would-be" Apples, Apollo computer seemed to be the best choice.

    Based in Chelmsford, Massachusetts, Apollo was less than a year old and had only announced itself to the public a few weeks before the founders of Mentor Graphics began their initial meetings.

    At that time, Apollo's product only consisted of specifications on paper. But the team knew of the Apollo founders and knew they had a proven track record in computer design. From what they read, the Apollo computer would be
    unlike anything in the marketplace. It would combine the time-sharing capabilities of a mainframe computer with
    the raw processing power of a dedicated minicomputer. Each Apollo computer could stand alone as a powerful 32-bit general purpose workstation. Alternatively, a theoretically unlimited number of Apollos could be linked together to share information directly, avoiding the potential bottleneck of passing data through a mainframe. Apollo called this concept the Domain network.

    In March, 1981, Apollo was only a promise, both as a product and as a company. Would the company deliver? Would it deliver on time? Would it back what it built? Would it be around tomorrow? Wouldn't it make more sense to go with an established and respected computer company like Hewlett-Packard or Digital Equipment Corporation?

    It would have been very difficult to put a start-of-the-art CAE product on any other workstation. So Mentor Graphics went with Apollo.


    The Birth of CAE


    The Mentor Graphics team had arrived at the product it would manufacture by surveying engineers across the country as to their most significant needs. That was how they made the decision to go into CAE and, specifically to wed software for engineering design functions to a workstation. Mentor Graphics then continued to survey engineers for information about the most desirable features of CAE capability. This was to be a critical advantage Mentor Graphics would enjoy in the competition against the companies that developed as its main rivals - Daisy Systems and Valid Logic.

    When Mentor entered the CAE market the company had two technical differentiators: The first was that Daisy and Valid Logic had "productized" software packages originally designed for other purposes. Valid Logic employed SCALD, a program developed at Lawrence Livermore Labs. Daisy's engineers had "front-ended" - that is, added steps to- a computer-aided design package. The difference between CAD and CAE were sufficiently distinct that prospective buyers saw Daisy's software as a hybrid and Valid Logic's as useful but not completely responsive to users' needs. Mentor, on the other hand, had designed its software from scratch, listening closely to what potential buyers told them about the special requirements of CAE. Engineers were impressed with the responsiveness of the software.

    Mentor's second advantage stemmed from the decision to use Apollo hardware as its platform. The state-of-the-art in CAE, such as it was, was based on the use of mainframe, timeshare CAD systems. There were severe weaknesses in this method. They were cumbersome and time-consuming to use. The graphics were not of the best quality. The Mentor Graphics simulator ran on a workstation instead of a mainframe, and was "interactive" so that, for the first time, an engineer could control the simulation as it ran.

    Targeting DAC 1982 for the product announcement, the company had less than a year from the time the engineers started in July 1981 to demonstrate capabilities no one else had been able to produce. Specifying the software tools began in the fall, after an initial period of learning the new Apollo computers that had arrived in August. What should happen was a matter of dispute when it came to product specs. The dispute boiled down to "technical excellence" versus "what customers need." Engineering argued for technically superior products, while marketing argued for products that customers needed and would buy. The synthesis produced something much better than would have been produced otherwise. The end result was a product that was technically formidable and also marketable.

    Conceiving a product was one thing, designing it another. Then there was building it. When 1982 rolled around, it was "put up or shut up". DAC was less than six months away, and as it turned out, literally every minute was needed for the company to produce software to demonstrate in Las Vegas. Hours and hours of work would lie ahead for the engineers. Thousands of lines of software code had to be written, programs had to be tested, and bugs had to be detected and fixed.

    Everybody at Mentor was performing heroically to set the stage for the company's first big public test. The product Mentor wanted to unveil, the system that came to be known as the IDEA 1000, was unprecedented. The Mentor Graphics team was trying to conceptualize, design and build a computer to build other computers. There was extant software for designing and simulating electronic circuitry, but the idea of integrating these two functions in a single database so that an engineer could sit at a single station and design both elements on one computer using one program was revolutionary. Before this development, schematics had been drawn by hand or "captured" on a computer. To simulate the design information the engineer had to use a mainframe. The idea of using a workstation in the Mentor Graphics configuration, the carefully selected Apollo machine, was a true innovation, one that promised great freedom and savings of time and money for engineering staff.


    DAC 1982


    As important as DAC is for Mentor Graphics today, it was practically of life-and-death magnitude in 1982. The company had a goal of shipping products by the fall of that year; to wait longer would be to risk jeopardizing an invaluable opportunity to blaze the trail in this new CAE market.

    The Mentor Graphics team crafted an unusual strategy for DAC, partly from necessity, partly out of shrewdness. The engineers were working overtime to turn the software into a single integrated system. All they had as the conference neared were pieces of a puzzle. They weren't sure the completed product would be ready by the date of the conference. A decision was made not to buy space on the convention hall floor, but to visit with participants in a hotel suite and give small demonstrations there.

    It wasn't until early June that the engineers began the task of integrating all the various software pieces into a single system and actually testing the applications. Leading up to DAC, the engineers were keeping track of problems on wrapping paper that extended from the ceiling to the floor in their conference room. As a bug was fixed, it was scratched off the list. There were new versions of the system being generated almost hourly. Every person who got on a plane for DAC carried floppy disks with the latest software.

    Parlaying a May 27, Electronic Design cover story on Mentor Graphics into a marketing tool, the team went to work. Around 4 a.m. on the Monday morning before DAC officially opened, the magazine article reprints, along with an invitation to the Mentor Graphics suite, were being slipped under hotel room doors at Caesar's Palace. Unable to determine which rooms the DAC attendees were staying in, the invitations were passed out indiscriminately. Vacationers and conference-goers alike were invited.

    Attendees began to trickle into the suite Monday morning for demonstrations. After the first presentations, word spread quickly through the exhibition floor that were was a company showing something never seen before - interactive simulation - in a hotel suite. By the close of DAC nearly a third to half of the 1,200 attendees had visited the suite and many were so impressed they wanted to buy a Mentor Graphics workstation immediately.

    Mentor Graphics was on its way to being an industry leader in the new market of CAE.


    Growth Through Innovation


    Since the early days, Mentor has expanded into a broad range of electronic design automation (EDA) product areas, including system level design, functional verification, emulation, IC physical design, PCB design and manufacturing, design-for-test and thermal analysis and design. In addition, Mentor has expanded into vertical EDA segments such as transportation systems design, as well as adjacent non-EDA segments such as embedded systems (realtime operating system, embedded middleware and user interface design).

    Besides expanding its scope into all aspects of technology design, Mentor has also innovated to keep up with new levels of complexity as integrated circuits went from a few thousand transistors to over a billion transistors in the latest microprocessors, graphics chips and SOCs (systems-on-chip). Mentor's tools have kept up with the new demands by taking advantage of the latest multicore and distributed computing architectures, allowing graphically decentralized teams to work collaboratively over networks, and enabling designers to model and validate entire systems before committing to implementation and to create and test software in parallel with hardware development.

    As the fabless-foundry model took over the eletronics industry, Mentor has worked ever closer with the IC foundries to ensure that fabless designers have a complete enabling tool flow that ensure successful designs that yield well even at the most advanced process nodes of 28nm and below.


    Still Going Strong


    In 2011 Mentor Graphics will celebrate its 30th anniversary, a major milestone for any company in the high tech industry, but especially significant with our years of growth as the surviving pioneer of an entirely new industry. Few high tech companies survive so long, let alone thrive.

    In 1981, three visionary managers and six engineers left another local entrepreneurial pioneer, Tektronix, to found not only a company, but a new industry. At the time, analysts categorized Mentor Graphics as a niche within the "computer aided design" market. In reality, the company was pioneering a new industry, the automation of electronic design, today known by its unique moniker "Electronic Design Automation".

    Over 30 years, Mentor Graphics has grown from a startup employing less than 100 in leased facilities in Beaverton, to a multinational company employing over 4,000. We occupy 300,000 square feet of office space on the Wilsonville campus with another 30 engineering sites and 70 sales offices around the world. The industry we pioneered is now $4 billion in size with MGC accounting for over $800M in sales.

    Mentor products have grown from relatively simple tools to some of the most sophisticated and complex commercial software applications that exist anywhere. Mentor software, combined with advances in hardware, has helped create the electronic revolution that has fueled the fires of innovation in countless industries. [post_title] => Mentor Company History [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => mentor-company-history [to_ping] => [pinged] => [post_modified] => 2010-10-21 07:28:00 [post_modified_gmt] => 2010-10-21 07:28:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/mentor-company-history.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 438 [post_author] => 28 [post_date] => 2010-10-15 18:34:00 [post_date_gmt] => 2010-10-15 18:34:00 [post_content] =>
    Again, my economic bellwether is TSMC, and judging by the first half, 2010 will go down as one of the most profitable years the semiconductor industry has ever seen. In the 2[SUP]nd[/SUP] quarter the foundries again posted record breaking wafer shipments, revenues, and profits. 3[SUP]rd[/SUP] quarter foundry financials should be even stronger. Bottom line, the semiconductor industry will see its largest yearly expansion and will easily break the $300B barrier in 2010.
    Pent up demand certainly explains the V recovery. My family was in financial lock down in 2009 but will more than make up the difference in 2010. New laptops, mobile phones, we even added a car and new energy efficient kitchen appliances, all semiconductor laden devices.


    Unfortunately, TSMC CEO Morris Chang recently commented that “inventory levels of its fabless and IDM customers have increased at a rate close to the increase in sales.” Total semiconductor inventories did grow 10% in Q2 which is double what was forecasted. Customers of both TSMC and UMC reported high inventory sequential growth levels for the second quarter of 2010:


    • Qualcomm’s grew 11%
    • Broadcom’s went up by 21.6%
    • MediaTek’s jumped 24%
    • AMD’s rose 14%
    • TI’s climbed 10%


    An August 5th post by Bill Jewel of Semiconductor Intelligence summarizes recent growth forecasts by the top analysts, which have risen dramatically month-to-month throughout 2010. Seriously, forecasting semiconductor growth this year has been like forecasting the weather, anything farther than 10 days out is just not reliable!

    Bill however does not exactly follow my semiconductor Boom to Bust prediction in 2011:
    Electronics new orders and production data from key countries also indicate a strong recovery.U.S.electronics new orders were up 14% in 2[SUP]nd[/SUP] quarter 2010 after showing a year-to-year decline of 14% in 2[SUP]nd[/SUP] quarter 2009. The European Union, Japan and Taiwan all had significant declines in electronics in early 2009, but have all bounced back to solid growth in 2010. China electronics production was the least affected by the recession, with 1[SUP]st[/SUP] quarter 2009 flat with a year ago. Chinahas recovered back to double-digit growth since 4[SUP]th[/SUP] quarter 2009.


    Nor does Bill support my position on growing semiconductor inventories:


    What about electronics inventories? Are they getting ahead of demand? Data from theU.S.andJapanshow the ratio of the inventory held by electronics manufacturers to their shipments began to climb in early 2008. The ratio peaked inJapanin December 2008 and then declined rapidly. In 2010, the ratio inJapanhas leveled off in the 80% to 90% range, below where it was in early 2008. TheU.S.ratio peaked in March 2009 and has declined to the 130% to 140% range, about the same level as the beginning of 2008.

    Unfortunately, government stimulus packages are expiring and leading economic indicators: consumer confidence index (CCI), jobs, housing, etc… are in decline, which supports my 2011 semiconductor bust (back to single digit growth) prediction. Not that there is anything wrong that!
    Hopefully the recent semiconductor foundry CAPEX surge will result in excess manufacturing capacity in 2012, which will in turn keep chip prices low. Remember, a modern GigaFab only has to run at 40% capacity to break even. Low chip prices will then support rampant consumerism and we will back to double digit semiconductor growth yet again. That’s my story and I’m sticking to it!


    lang: en_US

    [post_title] => Semiconductor Forecast: 2010 Boom – 2011 Bust? [post_excerpt] => [post_status] => publish [comment_status] => closed [ping_status] => closed [post_password] => [post_name] => semiconductor-forecast-2010-boom-2011-bust [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:37:24 [post_modified_gmt] => 2019-06-15 02:37:24 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/semiconductor-forecast-2010-boom-2011-bust.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 226 [post_author] => 18791 [post_date] => 2010-10-14 18:00:00 [post_date_gmt] => 2010-10-14 18:00:00 [post_content] => When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they hadn’t yet changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?

    What it really comes down to is this: if you tape out without these checks at 45/40 nm, you are taking a risk. If the design has yield issues and you didn’t run these checks, TSMC might wave the design off and insist that you take ownership of the yield issues. This is a huge risk. If the part comes out and has zero yield, and they find out it’s because of a level 1 hotspot in litho, or bridging due to CMP that you didn’t check for, then you have to eat the cost of a re-spin.

    Most design teams doing large designs count on a certain number of re-spins before full production anyway, but to have to do one before you have any functional parts is a disaster. If you get parts that yield, but yield poorly, it can be just as bad, because these things can take a long time to find using traditional Low Yield Analysis, or FA. As someone who once had to re-spin a custom design due to a flaw in the incoming spec, I know the worst thing management can ask you before a re-spin is, “Are you sure that’s all that’s wrong with the design?” That one is guaranteed to cause sleepless nights.

    At the time, TSMC pointed out that they had very little history on the 45/40 process and there was a definite need to do DFM analysis. TSMC also pointed out that DFM analysis might not be mandatory once the process is considered stable. By that time, the next process node will be in the hands of the early adopters, and DFM will be mandatory for that node, so the need for DFM won’t be going away anytime soon. The yield issues are real. Considering the total cost of developing a chip in 45/40 nm and the risks of really low yields, DFM tools seem like cheap insurance.

    – Simon Favre, Technical Marketing Engineer for Calibre YieldAnalyzer [post_title] => What Do You Mean by Mandatory? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => what-do-you-mean-by-mandatory [to_ping] => [pinged] => [post_modified] => 2010-10-14 18:00:00 [post_modified_gmt] => 2010-10-14 18:00:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/what-do-you-mean-by-mandatory.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 250149 [post_author] => 18791 [post_date] => 2010-10-14 18:00:00 [post_date_gmt] => 2010-10-14 18:00:00 [post_content] => When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they hadn’t yet changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?

    What it really comes down to is this: if you tape out without these checks at 45/40 nm, you are taking a risk. If the design has yield issues and you didn’t run these checks, TSMC might wave the design off and insist that you take ownership of the yield issues. This is a huge risk. If the part comes out and has zero yield, and they find out it’s because of a level 1 hotspot in litho, or bridging due to CMP that you didn’t check for, then you have to eat the cost of a re-spin.

    Most design teams doing large designs count on a certain number of re-spins before full production anyway, but to have to do one before you have any functional parts is a disaster. If you get parts that yield, but yield poorly, it can be just as bad, because these things can take a long time to find using traditional Low Yield Analysis, or FA. As someone who once had to re-spin a custom design due to a flaw in the incoming spec, I know the worst thing management can ask you before a re-spin is, “Are you sure that’s all that’s wrong with the design?” That one is guaranteed to cause sleepless nights.

    At the time, TSMC pointed out that they had very little history on the 45/40 process and there was a definite need to do DFM analysis. TSMC also pointed out that DFM analysis might not be mandatory once the process is considered stable. By that time, the next process node will be in the hands of the early adopters, and DFM will be mandatory for that node, so the need for DFM won’t be going away anytime soon. The yield issues are real. Considering the total cost of developing a chip in 45/40 nm and the risks of really low yields, DFM tools seem like cheap insurance.

    – Simon Favre, Technical Marketing Engineer for Calibre YieldAnalyzer [post_title] => What Do You Mean by Mandatory? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => what-do-you-mean-by-mandatory-2 [to_ping] => [pinged] => [post_modified] => 2010-10-14 18:00:00 [post_modified_gmt] => 2010-10-14 18:00:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/what-do-you-mean-by-mandatory-2.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 229 [post_author] => 18791 [post_date] => 2010-10-14 16:14:00 [post_date_gmt] => 2010-10-14 16:14:00 [post_content] => What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:

    Step 0 Commitment – Are you really sure you want to MV? Are you positive that multi-Vt & clock gating would not help with your power budgets? Proceed to step1 with caution only if you really must.

    Step 1 Architecture Selection – Ensure that the architecture is frozen and capture all the power constraints required for the chosen MV style in the UPF file. As most of you are aware this can also be done using the other power format but we will stick to UPF as it simplifies interoperability.

    Step 2 RTL Synthesis - Using the UPF file, complete RTL synthesis and derive the gate-level netlist. Ensure that the simulation & verification runs are complete and validated.

    Step 3 Data Import - Import LEF, lib, SDC, Verilog, and DEF. Properties that are relevant to the multi-voltage design flow are:
    • Special cells in Library (always_on, is_isolation_cell, is_isolation_enable, is_level_shifter)
    • Corner & modes – Define appropriate modes and corners for the different domains. Ensure that the worst case timing and power corners are setup correctly to concurrently optimize for power & timing.

    Step 4 Power Domain setup - Read the power domain definition by sourcing or loading the golden UPF file (same that was used for RTL synthesis). After reading the UPF file, the following items will be defined:
    • Domains with default power and ground nets
    • Power state table to define all possible power state combinations
    • Level shifter and isolation rules for the different voltage domains

    Step 5 Floorplanning - Create physical domains and the corresponding power structures for each individual supply net defined in the UPF. Define domain-specific hierarchy mapping and library association based on the architecture. Insert power switches for domains that are shut down (either VDD or VSS gated).

    Step 6 Power Domain Verification - Perform design checks for general design and UPF setup, verification of level shifters and isolation cells, and analysis of always-on connections. The intent here is to help you find any missing UPF or power domain setup data that could lead to potential misery.

    Step 7 Pre-CTS Opt - During the Pre-CTS flow, ensure that no port punching occurs on power domain interfaces. The optimization engine should use the power state table (PST) when buffering nets in a multi-voltage design to automatically choose always-on-buffers or otherwise. Nothing much you can do since you are the mercy of the tool.

    Step 8 CTS – During CTS, ensure that no port punching occurs on the power domains interfaces. Like the optimizer, the CTS engine should also use the PST-based buffering solution to determine the type of buffers to use while expanding the clock tree network. Some clock tree synthesis flows require special clock gate classes to be recognized in order to restrict sizing operations during CTS to equivalent class types. Have you been nice to your R&D lately?

    Step 9 Routing – Ensure that the routing engine honors the domain boundaries and contains the routes within them. Secondary power pin connections for special cells such as always-on buffers and level shifters should also be handled using special properties set on the power pins. Many design flows also require double vias and non-default width wires for routing of the secondary power connections. Top level nets that span across domains can be handled using gas stations to help optimize timing and area. Hail Mary…

    Step 10 Hope and Pray – This step is optional. If your chip is DOA start from step 0 and repeat until you either have a working part or are unemployed.

    --Arvind Narayanan, Product Marketing Manager, Place and Route Product Line [post_title] => How to Multi-Voltage IC Design in 10 Easy Steps [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => how-to-multi-voltage-ic-design-in-10-easy-steps [to_ping] => [pinged] => [post_modified] => 2010-10-14 16:14:00 [post_modified_gmt] => 2010-10-14 16:14:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/how-to-multi-voltage-ic-design-in-10-easy-steps.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 230 [post_author] => 18791 [post_date] => 2010-10-14 16:14:00 [post_date_gmt] => 2010-10-14 16:14:00 [post_content] => Clock designers are an enigma. Clock designers in general are die hard Star Wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in the peak of summer, and have like-minded clock designers as best lunch buddies. Clock designers are notorious for making lesser designers cry with their fancy PLL spice runs, non-negotiable skew numbers, and hogging higher layer metals. Clock designers live and breathe Picoseconds & watts (more recently) while the lesser mortals are perfectly happy to go for beers after two optimization runs. I have never been a clock designer myself but I have worked with clocks & clock designers for the longest time in my career, first as a design engineer, poring over timing reports and then as an application engineer supporting a sign-off timing tool. Building a good, well-balanced clock tree and effectively managing clock skew has been a challenge since the first transistor was invented and it still is today, especially at 28 & 22nm. The only difference is that now power is in the mix along with timing, which complicates things even more. At smaller technology nodes, the clock network is responsible for more than half of the power consumed and the majority of it is dynamic power due to the toggling clock.

    As we are all aware, clocks are a significant source of dynamic power usage, and clock tree synthesis (CTS) and optimization is a great place to achieve power savings in the physical design flow. The traditional low-power CTS strategies include lowering overall capacitance, specifically leaf caps, minimizing switching activity, and minimizing area and buffer count in the clock tree.
    While the traditional techniques help optimize clock tree power to a certain extent, using multi-corner multi-mode (MCMM) CTS is an absolute must for achieving optimal QoR for both timing and power. One of the biggest challenges of design variation is clock tree synthesis. In smaller nodes, large variations of resistance seen across various process corners pose additional challenge of balancing the clock skew across multiple corners. With the proliferation of mobile devices, clock trees have become extremely complex circuits with different clock tracing per circuit mode of operation. Further, building robust clock trees that can withstand process variation is a huge challenge for the design teams.

    Getting the best power reduction from CTS depends on the ability to synthesize the clocks for multiple corners and modes concurrently in the presence of design and manufacturing variability. Multi-corner CTS can measure early and late clock network delays over all process corners concurrently with both global and local variation accounted for. A multi-corner dynamic tradeoff between either buffering the wire or assigning it to less resistive layers is essential in order to achieve the best delay, area, and power tradeoff. In comparison to the 1M1C flow, the MCMM CTS solution provides significant reduction in area, buffer count, skew, TNS, and WNS in addition to lower dynamic power.

    Now, before I forget, let me state what I wanted to in the first place—I have to confess that I can now relate to this unique breed of clock designers and have utmost respect them for solving some of the most difficult chip design challenges thrown at them. A whole new generation is evolving with much cooler phones and Gore-Tex jackets.

    --Arvind Narayanan, Product Marketing Manager, Place and Route Product Line [post_title] => Clocks Will Be Clocks [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => clocks-will-be-clocks [to_ping] => [pinged] => [post_modified] => 2010-10-14 16:14:00 [post_modified_gmt] => 2010-10-14 16:14:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/clocks-will-be-clocks.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 231 [post_author] => 18791 [post_date] => 2010-10-14 16:14:00 [post_date_gmt] => 2010-10-14 16:14:00 [post_content] => Resistance is futile. I recently caved and switched to an iPhone after having been a loyal Google phone user for more than year. Apart from the coolness factor, my main motivation was corporate mail support that was absent in Gphone, plus the fact that I got the iPhone for free when my wife upgraded hers. The difference is day and night between the two phones - The iPhone UI is much friendlier, menu options are simple and logical and the device is much faster for certain applications like browsing, data download, and video capture. Most of the modern smart phones/PDA are increasingly employing the multi-voltage technique, specifically ‘dynamic voltage and frequency scaling’ (DVFS) to reduce power without sacrificing performance. The iPhone designers, unlike the Gphone have done a good job of creating this balance between the different applications running on the device.

    Regardless of the phone type multi-voltage designs, unlike the vanilla designs, are difficult to implement because of the inherent complexity and the need to handle special cells such as level shifters and isolation cells. In addition, these design styles also cause the number of modes and corners to increase significantly when min/max voltage combinations from all the power domains are considered. Because each different voltage supply and operational mode implies different timing and power constraints on the design, multi-voltage methodologies cause the number of design corners to increase exponentially with addition of each domain or voltage island. DVFS further complicate matters with varying frequency and clock combinations leading to even more design modes and corners. Additionally, the worst case power corners don’t necessarily correspond to the worst case timing, so it’s critical to know how to pick a set of corners that will result in true optimization across all design objectives without excessive design margins.

    So, what’s the story you might ask? It’s pretty simple (or not). In order to effectively close these multi-voltage designs across all modes, corners, timing, and power must be concurrently analyzed and optimized simultaneously for different combinations of library models, voltages, and interconnect (RC) corners. In essence, true and concurrent multi-corner multi-mode (MCMM) analysis and optimization is a pre-requisite for any multi-voltage design. Anything less would not guarantee convergence because optimization in one scenario could create a new violation in a different scenario, lead to multiple iterations, create unpredictable ECO loops, result in poor QoR and possibly reduce yield. In other words, low power designs, specifically MV designs, inherently require true MCMM optimization for both power and timing.

    Now, will I go back to the Gphone? If and only if they support corporate mail and also improve the performance. It wouldn’t hurt to jack up the coolness factor either. Till then I will remain an iPhone user (loyal or not is debatable). The only problem with the iPhone is, quoting Seinfeld, “if you are mad at someone you cannot slam the iPhone, but instead you will have to slide the phone off.”

    --Arvind Narayanan, Product Marketing Manager, Place and Route Product Line [post_title] => Why Only MV When You Can MC, MM & MV? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => why-only-mv-when-you-can-mc-mm-mv [to_ping] => [pinged] => [post_modified] => 2010-10-14 16:14:00 [post_modified_gmt] => 2010-10-14 16:14:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/why-only-mv-when-you-can-mc-mm-mv.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 250152 [post_author] => 18791 [post_date] => 2010-10-14 16:14:00 [post_date_gmt] => 2010-10-14 16:14:00 [post_content] => What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:

    Step 0 Commitment – Are you really sure you want to MV? Are you positive that multi-Vt & clock gating would not help with your power budgets? Proceed to step1 with caution only if you really must.

    Step 1 Architecture Selection – Ensure that the architecture is frozen and capture all the power constraints required for the chosen MV style in the UPF file. As most of you are aware this can also be done using the other power format but we will stick to UPF as it simplifies interoperability.

    Step 2 RTL Synthesis - Using the UPF file, complete RTL synthesis and derive the gate-level netlist. Ensure that the simulation & verification runs are complete and validated.

    Step 3 Data Import - Import LEF, lib, SDC, Verilog, and DEF. Properties that are relevant to the multi-voltage design flow are:
    • Special cells in Library (always_on, is_isolation_cell, is_isolation_enable, is_level_shifter)
    • Corner & modes – Define appropriate modes and corners for the different domains. Ensure that the worst case timing and power corners are setup correctly to concurrently optimize for power & timing.

    Step 4 Power Domain setup - Read the power domain definition by sourcing or loading the golden UPF file (same that was used for RTL synthesis). After reading the UPF file, the following items will be defined:
    • Domains with default power and ground nets
    • Power state table to define all possible power state combinations
    • Level shifter and isolation rules for the different voltage domains

    Step 5 Floorplanning - Create physical domains and the corresponding power structures for each individual supply net defined in the UPF. Define domain-specific hierarchy mapping and library association based on the architecture. Insert power switches for domains that are shut down (either VDD or VSS gated).

    Step 6 Power Domain Verification - Perform design checks for general design and UPF setup, verification of level shifters and isolation cells, and analysis of always-on connections. The intent here is to help you find any missing UPF or power domain setup data that could lead to potential misery.

    Step 7 Pre-CTS Opt - During the Pre-CTS flow, ensure that no port punching occurs on power domain interfaces. The optimization engine should use the power state table (PST) when buffering nets in a multi-voltage design to automatically choose always-on-buffers or otherwise. Nothing much you can do since you are the mercy of the tool.

    Step 8 CTS – During CTS, ensure that no port punching occurs on the power domains interfaces. Like the optimizer, the CTS engine should also use the PST-based buffering solution to determine the type of buffers to use while expanding the clock tree network. Some clock tree synthesis flows require special clock gate classes to be recognized in order to restrict sizing operations during CTS to equivalent class types. Have you been nice to your R&D lately?

    Step 9 Routing – Ensure that the routing engine honors the domain boundaries and contains the routes within them. Secondary power pin connections for special cells such as always-on buffers and level shifters should also be handled using special properties set on the power pins. Many design flows also require double vias and non-default width wires for routing of the secondary power connections. Top level nets that span across domains can be handled using gas stations to help optimize timing and area. Hail Mary…

    Step 10 Hope and Pray – This step is optional. If your chip is DOA start from step 0 and repeat until you either have a working part or are unemployed.

    --Arvind Narayanan, Product Marketing Manager, Place and Route Product Line [post_title] => How to Multi-Voltage IC Design in 10 Easy Steps [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => how-to-multi-voltage-ic-design-in-10-easy-steps-2 [to_ping] => [pinged] => [post_modified] => 2010-10-14 16:14:00 [post_modified_gmt] => 2010-10-14 16:14:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/how-to-multi-voltage-ic-design-in-10-easy-steps-2.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 486 [post_author] => 28 [post_date] => 2010-10-24 12:58:00 [post_date_gmt] => 2010-10-24 12:58:00 [post_content] => First of all it was not a rant, it was a clearly scripted rebuttal to the competitive pressures Apple is feeling from Android (here). As I blogged before, Apple is the Open Standards Antichrist and is trying to monopolize the trillion dollar mobile internet ecosystem with a CLOSED platform. According to Steve Jobs, “Open systems don’t always win.” Say what!?!?!?

    At the heart of the issue is the mobile operating systems Apple iOS and Google Android, so lets not forget the operating system wars of the 1980’s and 1990’s. Berkley UNIX Versus System V, which is today LINUX, a truly open system supported by all. I’m not saying it’s going to be a smooth ride for Android 3.0 integrators but open operating systems will prevail, believe it. Mac OS versus Windows, right? Steve Jobs can rant all he wants but in the end it is our vote that counts, which is why I don’t own a Mac, iPhone or iPad. DOWN with tyrany! Vote for FREEDOM of choice! Vote for the GINGERBREAD man!

    Coincidently, the Silicon Integration Initiative (Si2) Open Access Conference was last week to which I was cordially invited. I mention this not just because it included a free lunch (I blog for food), it is also something I feel is critical to the future of the semiconductor design ecosystem. Richard Goering already did a nice write-up (here) so I will skip right to the most critical Open Standards issue facing semiconductor design today, the Process Design Kit TUG OF WAR!

    The PDK is the contract between fabless semiconductor companies and the foundries containing the secret sauce of semiconductor manufacturing. The information inside a PDK is worth billions of dollars so it is protected accordingly. Unfortunately EDA tools require this information as well so EDA companies are the cheese in this symbiotic grilled cheese sandwich. Since EDA companies work with all of the foundries the opportunity for secret sauce leaks is always there. Since EDA companies try to get their proprietary formats into PDKs to lock in customers there will never be peace and harmony within the OpenPDK or IPL initiatives.

    In my humble but expert opinion PDKs should be treated like a platform with apps, not unlike the smartphone, tablet PC, and now big screen TVs. Unfortunately it will take a company with the market share of an Apple, Google, or Samsung to be successful with this type of platform/app strategy. Fortunately we have such a company in the semiconductor industry and that, of course, is TSMC.

    The TSMC iPDK (interoperable process design kit) initiative was announced on 7/21/2009 for 65nm and below. By keeping EDA vendors on TOP of the platform, TSMC can guard the secret sauce while sharing it with early access (top tier) fabless semiconductor companies. By lowering the cost of design apps, emerging fabless semiconductor companies can flourish. By keeping proprietary EDA formats OUT of the iPDK, TSMC can give customers the FREEDOM of choice!

    Of course this gives TSMC the opportunity to monopolize the market so the OpenPDK initiative must also adopt a platform strategy and serve as a counter balance to iPDK. Use the comment section to voice your opinion on this very sensitive but crucial topic. Semiconductor design ecosystem decision makers and influencers subscribe to my blog, absolutely. [post_title] => Steve Jobs’ 5 Minute Anti Open Systems Rant! [post_excerpt] => [post_status] => publish [comment_status] => closed [ping_status] => closed [post_password] => [post_name] => steve-jobs-5-minute-anti-open-systems-rant [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:37:26 [post_modified_gmt] => 2019-06-15 02:37:26 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/486-steve-jobs-5-minute-anti-open-systems-rant/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 7357 [max_num_pages] => 736 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => 1 [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_favicon] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => c5112d8f72264c3689e55a9b9b2a84fb [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => [tribe_controller] => Tribe\Events\Views\V2\Query\Event_Query_Controller Object ( [filtering_query:protected] => WP_Query Object *RECURSION* ) )
  • Steve Jobs’ 5 Minute Anti Open Systems Rant!

    Steve Jobs’ 5 Minute Anti Open Systems Rant!
    by Daniel Nenni on 10-24-2010 at 12:58 pm

    First of all it was not a rant, it was a clearly scripted rebuttal to the competitive pressures Apple is feeling from Android (here). As I blogged before, Apple is the Open Standards Antichrist and is trying to monopolize the trillion dollar mobile internet ecosystem with a CLOSED platform. According to Steve Jobs, “Open systems… Read More


    Semiconductor Supply and Demand in 2010/2011

    Semiconductor Supply and Demand in 2010/2011
    by Daniel Nenni on 10-22-2010 at 6:41 pm


    The semiconductor analysts are at it again, revising numbers, polishing their guesstimates, and patting each other on the back for being equally as inaccurate. I blame these crystal ball hacks for the semiconductor shortages and price hikes we are experiencing today.

    These people get paid to guide investors, and the industry… Read More


    Semiconductor Forecast: 2010 Boom – 2011 Bust?

    Semiconductor Forecast: 2010 Boom – 2011 Bust?
    by Daniel Nenni on 10-15-2010 at 6:34 pm


    Again, my economic bellwether is TSMC, and judging by the first half, 2010 will go down as one of the most profitable years the semiconductor industry has ever seen. In the 2[SUP]nd[/SUP] quarter the foundries again posted record breaking wafer shipments, revenues, and profits. 3[SUP]rd[/SUP] quarter foundry financials should… Read More


    What Do You Mean by Mandatory?

    What Do You Mean by Mandatory?
    by glforte on 10-14-2010 at 6:00 pm

    When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” … Read More


    What Do You Mean by Mandatory?

    What Do You Mean by Mandatory?
    by glforte on 10-14-2010 at 6:00 pm

    When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” … Read More


    How to Multi-Voltage IC Design in 10 Easy Steps

    How to Multi-Voltage IC Design in 10 Easy Steps
    by glforte on 10-14-2010 at 4:14 pm

    What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:… Read More


    Clocks Will Be Clocks

    Clocks Will Be Clocks
    by glforte on 10-14-2010 at 4:14 pm

    Clock designers are an enigma. Clock designers in general are die hard Star Wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in the peak of summer, and have like-minded clock designers as best lunch buddies. … Read More


    Why Only MV When You Can MC, MM & MV?

    Why Only MV When You Can MC, MM & MV?
    by glforte on 10-14-2010 at 4:14 pm

    Resistance is futile. I recently caved and switched to an iPhone after having been a loyal Google phone user for more than year. Apart from the coolness factor, my main motivation was corporate mail support that was absent in Gphone, plus the fact that I got the iPhone for free when my wife upgraded hers. The difference is day and night… Read More


    How to Multi-Voltage IC Design in 10 Easy Steps

    How to Multi-Voltage IC Design in 10 Easy Steps
    by glforte on 10-14-2010 at 4:14 pm

    What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:… Read More