Using a virtual prototype for your SoC design is accepted, conventional wisdom today because it can save development time by eliminating design iterations and avoid costly bugs that will cause an expensive product recall. In order to simulate your virtual prototype you need models, so a major question has always been, “Where… Read More
Physically Aware Synthesis
Yesterday Cadence had their annual front-end summit, the theme of which was physically aware design. I was especially interested in the first couple of presentations about physically aware synthesis. I joined Cadence in 1999 when they acquired Ambit Design Systems. One of the products that we had in development was called PKS… Read More
What Makes A Designer’s Day? A Bottleneck Solved!
In an environment of SoCs with tough targets of multiple functionalities, smallest size, lowest power and fastest performance to achieve within a limited design cycle window in order to meet the rigid time-to-market requirements, any day spent without success becomes very frustrating for a designer. Especially during tape-out… Read More
3D: Atlanta and Burlingame
Two conferences on 3D, one just over and one coming up next week. The one that was just over was hosted by Georgia Tech, the 3rd Annual Global Interposer Technology Workshop (GIT). I wasn’t there but my ex-colleague from VLSI Technology Herb Reiter was. Herb has become very much associated with all things 3D since he led the … Read More
A Brief History of DSP…Not By Any of Us
I came across an interesting article by Will Strauss which is pretty much the history of DSP in communication chips. Having lived through the early part of the history while I was at VLSI Technology I found it especially interesting.
At VSLI, our first GSM (2G, i.e. digital not analog air interface) was a 5-chip chipset. The DSP functionality… Read More
SPICE Development Roadmap 2013!
The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual autumn compact modeling workshop on Sept. 20, 2013 as an integral part of the ESSDERC/ESSCIRC Conference in Bucharest (RO). The event received full sponsorship from leading industrial partners including Agilent… Read More
Intel Comes Clean on 14nm Yield!
Hopefully this blog will result in a meaningful discussion on truth and transparency, and how Intel can do better in regards to both. Take a close look at the manufacturing slides presented by William Holt, Executive Vice President General Manager, Intel Technology and Manufacturing Group. You can see the slide deck HERE. Slide… Read More
Cadence & ARM Optimize Complex SoC Performance
Now a day, a SoC can be highly complex, having 100s of IPs performing various functionalities along with multi-core CPUs on it. Managing power, performance and area of the overall semiconductor design in the SoC becomes an extremely challenging task. Even if the IPs and various design blocks are highly optimized within themselves,… Read More
Webinar: Parasitic Debugging made easy!
We cordially invite you to attend this webinar and learn how to quickly debug post layout designs. Concept Engineering is a privately held company based in Freiburg, Germany. It was, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test … Read More
And the 2013 Mobile Winner is … Micron?
To the surprise of nearly all observers and due to no extraordinary technological advancement, there is one true mobile winner of the past year and that is Micron, whose stock has soared in 2013 from $5 to $21. I know, you’re probably saying, “Micron, you can’t be serious.” Let’s run through the … Read More
Real men have fabs!