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Intel’s 35% Density Advantage Claim Explored

Intel’s 35% Density Advantage Claim Explored
by Daniel Nenni on 09-20-2014 at 1:00 pm

The previous blog I did on the density difference between Intel 14nm and TSMC 20nm caused quite a stir and many interesting comments which I would like to address. After writing thousands of blogs on a wide variety of topics I have found that playing the devil’s advocate stimulates the most productive conversations and in this case it proved to be true. The Intel Core M vs Apple A8! blog went viral last week and resulted in some very interesting points made in the comment section that I feel should be explored in greater detail.

First is how we measure density. The semiconductor industry is all about packing more transistors in a smaller space. It is part of Moore’s Law, it is how we get less expensive consumer electronics, it is a badge of honor really. There are two transistor numbers you can use: the number of transistors in a design schematic and the number of transistors in the final layout which is then manufactured. The difference between these numbers varies but after taking a quick poll amongst leading edge design and layout people the range is 0-10% more transistors in the layout. Since density is a badge of honor most companies use the layout transistor count but if it serves a marketing purpose they will use the schematic transistor count. Either way, considering the point I’m trying to make, it doesn’t really matter.

Second, comparing the Intel Core M processor and the Apple A8 SoC is like comparing an orange to an apple but this is the only data we have today and it is a good starting point for a density discussion. The architectures are different (CPU vs SoC), the processes are different (20nm planar vs 14nm FinFET), and the companies are very different (IDM versus Fabless).

Third, the performance, power, and functionality of the chips are not part of this discussion. Tear downs and third party benchmarks will be required and they are not available yet. When they are, we can look back on this discussion and see if we were right and if not we can see where we went wrong. All in the interest of science, right?

Here is the argument: Intel claimed a 35% density advantage over TSMC during their November 2103 Investor Meeting using the middle slide above. Intel also used the Altera slide as support for their claim. TSMC rebuffed that claim during a quarterly conference call using the slide on the left.

According to Apple the A8, which is manufactured by TSMC on a 20nm planar process, has about 2B transistors on a 89mm2 die. According to Intel the Core M manufactured on a 14nm FinFET process has about 1.3B transistors on an 82mm2 die.

Given that:


  • According to TSMC, 16nmFF+ has a 15% density advantage over 20nm planar
  • We do not know what type of transistor count Intel and Apple uses but assume the worst case with a 10% variance (upsize Intel by 10%)

    Intel’s 35% density advantage claim just does not hold up, not even close. Time will tell, silicon does not lie, but for now TSMC’s density slide is much more honorable than Intel’s. And let’s not forget that Intel’s processes are highly specialized for a single product and TSMC’s processes serve a much wider range of applications. If true, this lack of density gap is really big news for the fabless semiconductor ecosystem, absolutely!

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