SoC designers can code RTL, run logic synthesis, perform place and route, extract the interconnect, then simulate to measure power values. Though this approach is very accurate, it’s also very late in the implementation flow to start thinking about how to actually optimize a design for the lowest power while meeting all… Read More
Sarcina Teams with Keysight to Deliver Advanced PackagesAll aspects of semiconductor design and manufacturing require…Read More
The Git Dilemma: Is Version Control Enough for Semiconductor Success?Git is a version control system that saves…Read More
TSMC Responds to Intel’s 14nm Density Claim!
TSMC responded to Intel’s 14nm density advantage claim in the most recent conference call. It is something I have been following closely and have written about extensively both publicly and privately. Please remember that the fabless semiconductor ecosystem is all about crowd sourcing and it is very hard to fool a crowd of semiconductor… Read More
Semiconductor IP and Correct-by-construction Workspaces
SoC hardware designers could learn a thing or two from the world of software development, especially when it comes to the topic of managing complexity. Does that mean that hardware designers should literally use a software development environment, and force fit hardware design into file and class-based software methodologies?… Read More
DSPs converging on software defined everything
In our fascination where architecture meets the ideas of Fourier, Nyquist, Reed, Shannon, and others, we almost missed the shift – most digital signal processing isn’t happening on a big piece of silicon called a DSP anymore.
It didn’t start out that way. General purpose CPUs, which can do almost anything given enough code, time,… Read More
Happy Birthday GSA
This year marks the 20th anniversary of GSA and collaboration around the foundry and fabless ecosystem. Originally GSA was FSA, the fabless semiconductor association. There was a semiconductor associations 20 years ago, the SIA, but that was still the “real men have fabs” era and fabless semiconductor companies… Read More
Smart Clock Gating for Meaningful Power Saving
Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More
Digital @ Nano-Scale while Analog Hovers @ 65nm and Above
Who’s going to DesignCon next week? I am, absolutely. Dr. Hermann Eul, Vice President & General Manager, Mobile & Communications Group, Intel Corporation will be keynoting on Tuesday. This one I want to hear! Intel missed mobile at 32nm, 22nm, and 14nm. Lets see what they have planned for 10nm. Something good I hope!… Read More
The Semiconductor Landscape – III
In continuation to my earlier observations and anticipations (landscape1, landscape2) which came up to my expectations, I was further inspired to ponder over the macros of our ever growing semiconductor industry. We may argue the business is stagnating, we may argue that the pace of scaling is slowing, but when I look back at the… Read More
SilabTech Awarded 2013 Best Start-up in India
This is obviously great news for SilabTech, and this is the type of news which will change the perception that we (non-Indian) have of the Semiconductor industry in India. About 15-20 years ago, the India Embedded/VLSI industry was perceived as low cost design resource pool, a good place where to implement design center. The hidden… Read More
Intel is NOT Transparent Again!
Recent headlines suggest that Intel was not transparent about some of the products they showed at the CES keynote. Intel confirmed on Friday that they used ARM-based chips for some of the products but would not say which ones. When your company’s tag line is “Intel Inside” and you hold up a product during your keynote wouldn’t… Read More
Ncredible Nvidia