Semiwiki Ansys SimWorld

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                    [post_content] => While I was in Taiwan last month battling a Super Typhoon, Morris Chang was in Silicon Valley picking up his IEEE Medal of Honor. Gordon Moore, Andrew Grove, and Robert Noyce all have medals. The other winners, including 10 Nobel prize recipients, are listed HERE. An updated wiki on Dr. Morris Chang is located HERE.

The 12+ hour plane ride home gives a person plenty of time for reflection on why TSMC is so successful. Leadership is certainly important, just take a look at the executive staff on the new TSMC corporate website ( www.tsmc.com ). But in my opinion, TSMC's success boils down to one thing, they are a dedicated IC foundry that is dependent on its customers and ecosystem partners and TSMC has never forgotten that.

Foundry 2010 Revenues:
(1) TSMC $13B
(2) UMC $4B
(3) GFI $3.5B
(4) SMIC $1.5B
(5) Dongbu $512M
(6) Tower/Jazz $509M
(7) Vanguard $508M
(8) IBM $430M
(9) Samsung $420M
(10) MagnaChip $405M


But if you ask how TSMC and Dr. Morris Chang himself got where they are today it can be summed up in three words: Business Model Innovation. Other business model innovators include: eSilicon, ARM, Apple, Dell, Starbucks, Ebay, Google, etc…. I would argue that without TSMC some of these businesses would not even exist.

Morris Chang’s education started at Harvard but quickly moved to MIT as his interest in technology began to drive his future. From MIT mechanical engineering graduate school Morris went directly into the semiconductor industry at the process level and was quickly moved to management. After completing an electrical engineering PhD program at Stanford, Morris leveraged his process level semiconductor management success and went to Taiwan to head the Industrial Technology Research Institute (ITRI) which lead to the founding of TSMC.

In 1987 TSMC started 2 process nodes behind current semiconductor manufacturers (IDMs). Morris Chang made the first TSMC sales calls with a single brochure: TSMC Core Values: Integrity, commitment, innovation, partnership. 4-5 years later TSMC was only behind 1 node and the orders started pouring in. In 10 years TSMC caught up with IDMs (not Intel) and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing.

Morris Chang Awards



  • 1998, "Top 25 Managers of the Year" and "Stars of Asia" by Business Week.
  • 1998, "One of The Most Significant Contributors in the 50 years of Semiconductor Industry" by BancAmerica Robertson Stephens.
  • 2000, "IEEE RobertN. Noyce Award" for Exceptional Contributions to Microelectronics Industry.
  • 2000, "Exemplary Leadership Award" from the Fabless Semiconductor Association (GSA).
  • 2005, "Top 10 Most Influential Leaders of the World" by Electronic Business.
  • 2008, "Semiconductor Industry Association's Robert N. Noyce Award"
  • 2009, "EE Times Annual Creativity in Electronics Lifetime Achievement Award"
  • 2011, IEEE Medal of Honor

Dr. Morris Chang turned 80 on July 10[SUP]th[/SUP] 2011, I have seen him in Fab 12 but we have not met. Morris returned to the CEO job in June of 2009 and is still running TSMC full time as CEO and Chairman. He works from 8:30am to 6:30pm like most TSMC employees and says that a successful company life cycle is: rapid expansion, a period of consolidation, and maturity. The same could be said about Morris himself.

Here is a new 5 minute video from TSMC. I highly recommend watching it:

Pioneer of Dedicated IC Foundry Business Model

Related Blogs:TSMC 28nm / 20nm Update!




 [post_title] => TSMC and Dr. Morris Chang! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => tsmc-and-dr-morris-chang [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:11 [post_modified_gmt] => 2019-06-15 02:40:11 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/tsmc-and-dr-morris-chang.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 754 [post_author] => 3 [post_date] => 2011-09-05 15:37:00 [post_date_gmt] => 2011-09-05 15:37:00 [post_content] => Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented as a number between 0 and 1.





An example is shown above where an enclosure rule is described as:M1 minimum overlap past CA for at least two opposite sides with the other two sides >= 0.00um (Rectangular enclosure).

The top Metal line has a Via with short overlap and its score is about 0.4 (less manufacturable, lower yielding) while the bottom Metal line has a Via with a much longer overlap so its score is about 0.9 (more manufacturable, higher yielding).

When I first started designing full-custom ICs all of our rules were described as Pass/Fail, nothing ambiguous at all. Today however DRC rules are a different story at the 28nm node and lower because of DFM and lithography challenges, so IC designers need a new way to be warned about layout practices that impact yield early in the design process.

One way that GLOBALFOUNDRIES started describing the scoring on a rule was to provide two categories of rules: Low Priority and High Priority


MCD Scoring Model









The blue line on the top is for Low Priority rules and the X axis represents the Score, while the slope of the line gradually moves downward. In contrast the High Priority rule line shown in red has a much steeper slope, meaning that it's score approaches Zero more quickly.

With just these two rule lines we can bound all of the DRC rules in our process by placing each rule into one of two categories: High or Low priority.

An improvement over the MCD scoring model is called the MAS scoring model where each DRC rule has its own slope based on actual Silicon measurements:


MAS Scoring Model










The green and grey lines correspond with two DRC rules that have been measured and plotted.

This new MAS Scoring Model is support by Mentor's Calibre CFA tool:



In this dialog I can see the MAS score for each DFM rule and then decide if I want to edit my layout to improve the score.



Many process effects are covered by the MAS score: litho, stress, charging, random particle defect, etc.

I can now sort and rank which DFM layout issues to work on first.

Summary
GLOBALFOUNDRIES is using DFM scoring to qualify IP at the 65nm and smaller nodes as a means to improve quality. Mentor Calibre tools use the equation-based MAS and litho friendly design so that a designer can converge more quickly on DFM fixes in their IP.








[post_title] => Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => manufacturing-analysis-and-scoring-mas-globalfoundries-and-mentor-graphics [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:10 [post_modified_gmt] => 2019-06-15 01:53:10 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/manufacturing-analysis-and-scoring-mas-globalfoundries-and-mentor-graphics.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 753 [post_author] => 4 [post_date] => 2011-09-05 04:53:00 [post_date_gmt] => 2011-09-05 04:53:00 [post_content] => Even if nSys acquisition by Synopsys will not have a major impact on Synopsys’ balance sheet, it is a kind of earthquake in the Verification market landscape. After the Denali acquisition by Cadence in 2010, nSys was most probably the market leader in verification IP, if we look at the independent VIP providers (excluding Cadence). The company VIP port-folio can bear the comparison with Cadence, as nSys supports: PCI family, Communication standards, Storage Interfaces, USB Port, DDR3/2 Memory Controller, MIPI, AMBA and some miscellaneous interfaces. nSys being privately owned, we don’t know the company revenue, neither if the company is profitable. Was this acquisition an “asset sale”, and just an opportunistic deal closed by Synopsys at low cost, with the side effect to compete directly with Cadence in a market where the company has heavily invested during the last three years? Or the goal is to consolidate Synopsys position in the Interface IP market, where the company is the dominant provider, present, and leader, in every segment (DDRn, PCIe, USB, SATA, HDMI, MIPI…), by adding “independent” VIP to the current offer?



Synopsys was offering “bundled” VIP, and this is not the best way to valorize the product, as the Design IP customer expect to get a bundled VIP almost for free. If Synopsys acquisition of nSys illustrates a real strategy inflection, another side effect will be the lack of accuracy of the “Yalta description”: Cadencedominant in VIP and Synopsysin IP market!

Only Synopsys and nSys management teams know the answer. Today we only can evaluate the impact of this acquisition on the day to day life of SoC design teams, when this SoC integrates an Interface IP... which happen in most of the cases.

I found an interesting testimonial on nSys web site: "We had debated using bundled VIP solutions, which were available with PCIe IP, but after evaluating the nSys Verification IP for PCIe, we dropped the idea. We were impressed by the level of maturity of the PCIe nVS. We also realized that the PCIe nVS provided us with the ability to do independent verificationof the IP that could not have been achieved with the bundled models. The nSys solution has helped our engineering team increase productivity too." From Manoj Agarwal, Manager ASIC, EFI.

The important word in this testimonial is “independent”. We have expressed this concern in the past, when saying:

“Common sense remark about the BFM and IP: when you select a VIP provider to verify an external IP, it is better to make sure that the design team for the BFM and for the IP are different and independent (high level specification and architecture made by two different person). This is to avoid the “common mode failure”, principle well known in aeronautic for example.”

A SoC project manager will have the option to buy an “independent” VIP to run the verification of the interface function… to the same vendor selling the IP. He still can buy it to the main competitor (Cadence) or to one of the remaining VIP provider (Avery, ExpertIO, PerfectVIP, Sibridge Technology, SmartDV Technology), but the one stop shop argument (buy the Controller, the PHY and the Verification IP together) will be reinforced, especially because the VIP comes now from a real independent source.

Is Synopsys acquisition of nSys an opportunistic asset sale? Honestly I don’t know, but this is certainly a stone in Cadence’ garden (as the company has bought Denali in 2010 and products from Yogitech SpA, IntelliProp Inc. and HDL Design House in October 2008 to consolidate their VIP port-folio) and a threat for the remaining VIP provider. Is it good news for Synopsys customers? Yes, because the “one stop shop” will ease the procurement and technical support process. Synopsys customers should just make sure to buy at the right price… market consolidation can make life easier… and price higher!

Eric Estevefrom IPnest





 [post_title] => What changes to expect in Verification IP landscape after Synopsys acquisition of nSys? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => what-changes-to-expect-in-verification-ip-landscape-after-synopsys-acquisition-of-nsys [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:08 [post_modified_gmt] => 2019-06-15 01:53:08 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/what-changes-to-expect-in-verification-ip-landscape-after-synopsys-acquisition-of-nsys.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 752 [post_author] => 20367 [post_date] => 2011-09-04 19:36:00 [post_date_gmt] => 2011-09-04 19:36:00 [post_content] =>
In a Washington Post Column this past Sunday, Barry Ritholtz, A Wall St. Money Manager and who has a blog called the Big Picture, recounts the destruction that Apple has inflicted on a wide swath of technology companies (see And then there were none). He calls it “creative destruction writ large.” Ritholtz though is only accounting for what has occurred to date. I would contend that we are about to start round two and the changes coming will be just as significant. If I were to guess, HP will soon decide to Farm out its Server Business to Intel. Intel will soon realize that they will need to step up to the plate for a number of reasons.

When HP hired Leo Apotheker, the ex-CEO of Software Giant SAP, the Board of Directors (which includes Marc Andreessen and Ray Lane, formerly of Oracle) implicitly fired the flare guns that they were in distress and were going to make radical changes as they reoriented the company into the software sphere of the likes of Oracle and IBM. To do this, they had to follow IBM’s footsteps by first stripping out PCs. IBM, however, sold its PC group to Lenovo back in 2004 before the last downturn. Unfortunately for HP, it will get much less for its PC business than what they paid for Compaq.

The next step for HP is risky but necessary. They need to consolidate server hardware development under Intel. Itanium based servers are selling at a run rate of $500M a quarter at HP are now less than 5% of the overall server market compared to IBM Power and Oracle SPARC, which together account for nearly 30% of the server dollars. Intel and AMD x86 servers make up the rest (See the chart below). In addition, IBM’s mainframe and Power server businesses are growing while HP’s Itanium is down 10% year over year.

 Oracle’s acquisition of Sun always intrigued me as to whether it was meant as a short-term effort to force HP to retreat on Itanium or as a much longer-term strategy of giving away hardware with every software sale. When Oracle picked up Sun, it still held a solid #2 position in the RISC world, next to IBM. By taking on Sun, Oracle guaranteed SPARC’s survival and at the same time put a damper on HP growing more share. New SPARC processors were not falling behind Itanium as Intel scaled back on timely deliveries of new cores at new process nodes. More importantly, the acquisition was a signal to ISVs (Independent Software Vendors) to not waste their time porting apps to yet another platform, namely Itanium. Oracle made sure that HP was seen, as an orphaned child when it announced earlier this year that is was withdrawing support for Itanium.

There is only one architecture, at this moment, that can challenge SPARC and Power and it is x86. It is in HP’s interest to consolidate on x86 and reduce its hardware R&D budget. If needed, a nice software translator can be written to get any remaining Itanium apps running on x86. Since the latest XEON processors are three process nodes ahead of Itanium, there should be little performance difference. But what about Intel, do they want to be the box builder for HP?

I would like to contend that Intel has to get into the box business and is already headed there. There chief issue in holding them back is the reaction from HP, Dell and IBM. Neither of them is generating great margins on x86 servers. With regards to Dell, Intel could buy them off with a processor discount on the standard PC business, especially since they will now be the largest volume PC maker. IBM is trickier.

But why does Intel want to go into the server systems business. The answer is several fold. From a business perspective they need more silicon dollars as well as sheet metal dollars. Intel sees another $20-$30B opportunity in ramping up and they will need it to counteract any flatness or drop in processor business in the client side of the business. Earlier this year, Intel bought Fulcrum, if they build the boxes for the data center, then they have the potential to eat away at Broadcom’s $1B switch chip business.

A more interesting angle is the data center power consumption problem. Servers consume 90% of the power in a data center. It used to be that processors were the majority of the power, but with the performance gap growing between processors and DRAM and the rise of virtualization it now becomes a processor and memory problem. Intel is working on platform solutions to minimize power but they expect to get paid for their inventions.

Intel has started to increase prices on server processors based on reducing a data center’s power bill. Over the course of the next few years they will let processor prices creep up, even with the looming threat of ARM. This is a new value proposition that can be taken one step further. If they build the entire data center box with processors, memory, networking and eventually storage (starting with SSDs), then they can maximize the value proposition to data centers, who may not have alternative suppliers.

In some ways Intel is at risk if they just deliver silicon without building the whole data center rack. There are plenty of design groups at places like Google, Facebook and others who understand the tradeoffs of power and performance and would like to keep cranking out new systems based on the best available technology. By Intel putting down its big foot, it could eliminate these design groups and make it more difficult for a new processor entry (AMD or ARM based) from entering the game.




 [post_title] => HP Will Farm Out Server Business to Intel [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => hp-will-farm-out-server-business-to-intel [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:09 [post_modified_gmt] => 2019-06-15 02:40:09 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/hp-will-farm-out-server-business-to-intel.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 751 [post_author] => 9491 [post_date] => 2011-08-31 20:00:00 [post_date_gmt] => 2011-08-31 20:00:00 [post_content] =>  The CEO panel at the 2nd GTC wasn't especially enlightening. The theme was that going forward will require cooperation for success and everyone was really ready to cooperate.

The most interesting concept was Aart talking about moving from what he called "scale complexity" aka Moore's law to what he called "systemic complexity" where we are moving from the age where transistors are cheaper at each process generation to where you can build larger systems, but the per transistor cost will not be less.

Aart also had the most memorable image of the afternoon. He was talking about how amazing it is that you go to a fine-dining restaurant with 8 people and course after course things come to the table at the same time all perfectly prepared. My daughter's boyfriend is the chef of just such a restaurant so I know about it a bit from behind the scenes and it is still amazing. Delivering a foundry capability is like that: the process, the tools, the IP, the manufacturing ramp and everything else needs to all be ready at the same time. The output isn't the sum of the factors but the product, and if one is zero the whole thing is a big zero. Global Foundries' kitchen just happens to cost billions of dollars, a bit more than even the most over the top fine dining restaurant.

Mojy, who was chairing the session, had one question to try and break up the love-in. Global Foundries, IBM and Samsung all compete, and yet they cooperate in process development even going as far as fab-same implementation (same equipment etc in all the fabs of each company). Will the big EDA companies cooperate in the same way? Of course this is a bit of an unfair question. The only reason that semiconductor companies cooperate is that technology development has got too expensive for any one company (except Intel, always the exception) to do it alone as they would have done 15 years ago (and, indeed, did). While foundries and semiconductor companies get some differentiation through process, most comes from what they design (for IDMS) or how they service customers operationally (for foundries). The software that EDA companies create is their differentiation. If Cadence, Synopsys, Magma and Mentor cooperated to build a shared next generation place and route system then it is hard to see how they would differentiate themselves. Yes, some companies have better AEs, some have better geographic coverage in some places etc, but basically they would all be selling a product that they could only differentiate by price. Today, with unique systems but with broadly similar capabilities, they are already close to that situation. So the CEOs largely ducked the question since "no" would have been too direct an answer.




 [post_title] => I love you, you love me, we're a happy family... [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => i-love-you-you-love-me-were-a-happy-family [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:39:29 [post_modified_gmt] => 2019-06-15 01:39:29 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/i-love-you-you-love-me-were-a-happy-family.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 750 [post_author] => 9491 [post_date] => 2011-08-31 19:07:00 [post_date_gmt] => 2011-08-31 19:07:00 [post_content] =>  I went to the second Global Technology Conference yesterday. It started with a keynote by Ajit Manocha who is the CEO of about 2 months. I hadn't realized until someone asked him during the press lunch that he is technically only the "acting" CEO. Actually, given his experience he might be the right person anyway, rather than just a safe pair of hands in the meantime. He was Chief Manufacturing Officer for NXP (nee Philips Semiconductors) and so already has, as he put it, experience of running multiple fabs in multiple countries. When asked if he might become the permanent CEO he basically said that he'd advised the board to look for the best person possible. And then he added that, of course, if he didn't deliver he'd be out of a job anyway.

Ajit (and everyone at Global) makes a big deal about being globally distributed as opposed to clustered in one country like any companies using the "traditional model", such companies going unmentioned as if the mere mention of TSMC might lose business (oh, wow, I didn't know you had a competitor, I must give them a call). Of course the tsunami in Japan has made people more aware of how vulnerable supply chains are sometimes, and of course Taiwan also sits in earthquake country, not to mention political instability country if China's leaders decided to do something stupid. Global tries to have every process (the recent ones, anyway, the old ones are only in the old Chartered fabs in Singapore) in at least two of their fabs (Singapore, Dresden in the old East Germany, and the one under construction in upstate New York which is now ready for equipment install ahead of schedule).

Ajit talked mostly about getting closer to customers and being the vendor choice. Of course at some level everyone tries to do that and it is much easier to talk about than it is to achieve in practice. But here are a few interesting statistics: over 150 customers, over 11,000 employees and spending $8B on capex 2010-2011.

 The capacity they have in place is quite impressive. Fab 1 (the old AMD fab in Dresden) is expanding to 80,000 wafer starts per month. I assume that means 300mm wafers rather than 200mm wafer-equivalents that is sometimes used. The focus is 45/40/32/28nm. Fab 8 (under construction in New York) is big: 6 football fields of clean room with over 7 miles of overhead track for moving wafer transport vehicles around. It will have 60,000 wafer starts per month once ramped, focused on 28/20nm. And in Singapore (the old Chartered fabs) they have a lot of 200mm capacity and, in fab 7, 50,000 wafer starts per month anywhere from 130nm to 40nm.

The meat of what Global is up to was in Gregg Bartlett's presentation on the implementation of their process roadmap. He is very proud that they have gate-first 32nm HKMG ramped while other people using it are struggling. During the lunch he was asked about Intel's 3D transistor. He thinks that despite some advantages, they will prove very difficult to control in the vertical dimension and are too restrictive for a general foundry business. Which is interesting if true since Intel has more capacity than it needs and so is entering the foundry business!

At 28nm they will use basically the same FEOL (front end of line, i.e. transistors) as at 32nm, namely gate-first HKMG. Compared to 40nm this is a 100% density increase and either a 40% increase in performance or a 40% reduction in power (depending on how you take it). He reckons that die are 10-20% smaller relative to 28nm gate-last processes. That would be TSMC.

But apparently at 20nm, litho restrictions mean that you can no longer get that 10-20% benefit so they will switch to gate-last. Versus 28nm this is nearly a 50% area shrink and they are investing in innovation in interconnect technologies.

 And after that? 16/14nm. Multi-gate FinFET transistors, lots of innovation. Also innovation in EUV (extreme ultraviolet) where they have been doing lots of development work (over 60 masks delivered) and will have production installation in New York in the second half of next year.




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The economic news lately has been bleak. U.S. GDP grew at an anemic 0.4% in 1Q 2011 and 1.0% in 2Q 2011 – leading to increased concerns about a double-dip recession. High government debt levels in the U.S. and several European nations have contributed to volatile stock markets. The news does not seem to be any better for the semiconductor industry. According to the Semiconductor Industry Association’s (SIA) reporting of World Semiconductor Trade Statistics (WSTS) data, the semiconductor market declined 2% in 2Q 2011from 1Q 2011. The semiconductor market in 2Q 2011 was down 0.5% from a year ago after 8.2% year-to-year growth in 1Q 2011.

However the news is not all bad. Looking at the components of U.S. GDP, spending on electronics by consumers and business is still relatively strong. Business investment in equipment and software (including computers, telecom and manufacturing equipment) grew 8.7% in 1Q and 7.9% in 2Q. Consumer spending on recreational goods and vehicles (over 75% of this category is electronics) grew 15.3% in 1Q 2011 and 9.3% in 2Q 2011.




Key end markets for semiconductors are continuing to show solid growth. Total mobile phones grew at high double digit rates for the first two quarters of 2011, according to Gartner. Smartphones are driving mobile phone growth – with year-to-year growth of 85% in 1Q 2011 and 74% in 2Q. PCs declined 3.2% in 1Q 2011 versus a year ago but bounced back to 2.6% growth in 2Q, based on IDC data. Media tablets (dominated by Apple’s iPad) are growing explosively, with IHS iSuppli forecasting 245% growth in 2011. Media tablets are certainly displacing some PC sales, thus the combination of the two gives a better picture of demand. Total PC plus iPad shipments were up 7.7% from a year ago in 1Q and up 9.5% in 2Q.



What is the outlook for the semiconductor market for the rest of 2011? See more at:http://www.semiconductorintelligence.com/




 [post_title] => Economic news not all bad for semiconductors [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => economic-news-not-all-bad-for-semiconductors [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:06 [post_modified_gmt] => 2019-06-15 02:40:06 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/economic-news-not-all-bad-for-semiconductors.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 746 [post_author] => 20367 [post_date] => 2011-08-30 10:30:00 [post_date_gmt] => 2011-08-30 10:30:00 [post_content] =>  The complete destruction of the consumer PC market in the US and Europe is well within Apple’s grasp and will begin to unfold next summer. There is nothing that Intel, Microsoft or the retail channels can do to hold back the tsunami that was first set in motion with the iPad last year and comes to completion with the introduction of one more mobile product and the full launch of the iCloud service for all. The dollars that are left on the table to defend the onslaught are too insufficient to put up a fight. Collapse is at hand.

In the military realm there are plenty of examples of Wars that continue seemingly forever with no side able to gain the upper hand and then in just a matter of months - a sudden collapse due to lack of fighting men, shortages of food and armament and finally a realization that there is no home front left to defend. The American Civil War demonstrated no clear winner until late summer and fall of 1864, when General Sherman marched on Atlanta and then to Savannah, presenting the city to Lincoln as a Christmas present. Along the way he destroyed everything along a 50 mile wide by 250-mile path. Farms, crops, railroads, plantations and the railroad distribution channel were taken out leaving the confederate soldier with nothing to carry on the fight. Suddenly, a collapse.

The full range of Apple products in combination with the ever-expanding number of Apple stores (there are 339 worldwide stores with 56 more coming on line) is sucking the oxygen out of retailers like Best Buy who wonder what they will sell under the big roofs. PCs themselves were never a big profit center for the retailers. It was the accessories that offered huge profit margins. Things like mouses, carrying cases, earphones and especially service agreements were the money winners. But with customers now going to Apple Stores or Apple online, the accessory business moves to Apple. Without this business retailers cut back on the number of PCs they have on display which leads to a distribution problem for PC makers and a natural decline in PC sales.

But this is the least of the worries for PC makers and companies like Microsoft, Google and Intel because in one year Apple will split the MAC Air line to introduce a new product I will call the MAC Air – iCloud. Using the same skins as the MAC Air, the new mobile product with come with an A6 processor and an integrated 3G or 4G wireless solution for access to iCloud from anywhere. The underlying hardware will be similar to what is in an iPAD but with perhaps a little more DRAM to handle productivity Apps that are delivered to the device from the remote iCloud Servers that are x86 based. The MAC Air iCloud is a rendering machine for Office Apps that don’t run on the A6 processor. All other iOS apps will be available to the mobile device.

There are many rumors that Apple will switch the MAC Air to an A6 next year, but this will not be the case. Apple is not ready to take this step, yet. It will open the MAC Air business for bid between AMD and Intel with the bet that the processor cost will decline from $220 today to $75 by mid next year. Look for Intel to hold the business but give Apple the price break it needs to drop entry level MAC Air to $799 from $999 today. The volume will increase dramatically, killing off what is left of the $500-$1000 PC market.

The MAC Air – iCloud will come out at a $399 price for consumers that agree to pay a $25 per month service for at least 24 months in order to gain access to the Office Apps and storing data files on the cloud. Like the iPhone service plans, this one will pull in many customers that may have previously chosen a PC. If you look at the Best Buy data on their web site, the high volume runners all sell for <$449 and the majority sell for $349 - $449. This is the sweet spot of what is left of the consumer PC market. This is why Apple will stick their MAC Air iCloud right in between at $399.

For Microsoft and Intel, this is the end of their consumer market and the business model that sucks out the majority of the dollars. Microsoft still demands $30 per PC O/S royalties and Intel and AMD look to get at least $50-$60 per PC for the processor. With Apple moving customers over to iCloud they get to reap the margins of the entry level consumer who wants to join a better ecosphere that is more secure and offers better mobility and in the end much better, hands on customer support.

I have been in an apple store several times in the past few years for technical issues with my phone and MAC Book Pro. Aside from the time I accidently dropped a phone in a cup of water, Apple has offered free technical store and an iPhone replacement. It was only recently that it dawned on me how smart Apple is in their approach on service and in the end this draws in more customers that will pay more for the Apple protection.

Apple will coddle users even more with the iCloud based mobile devices. The retailers don’t stand a chance, which means the PC makers will see distribution channels shrivel. Microsoft, Google, Intel and the rest of the PC supply chain have to think of how to change their business model that gets them as close as a handshake away from their customer.





 [post_title] => Apple’s $399 Plan to Win Consumer Market in Summer 2012 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => apples-399-plan-to-win-consumer-market-in-summer-2012 [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:04 [post_modified_gmt] => 2019-06-15 02:40:04 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/apples-399-plan-to-win-consumer-market-in-summer-2012.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 745 [post_author] => 28 [post_date] => 2011-08-29 14:33:00 [post_date_gmt] => 2011-08-29 14:33:00 [post_content] =>  Verifying circuits on advanced process nodes has always been difficult, and it's no easier with today’s nanometer CMOS processes. There's a great paradox in nanometer circuit design and verification. Designers achieve their greatest differentiation when they implement analog, mixed-signal, RF and custom digital circuitry on a single nanometer CMOS die, running at GHz frequencies. Yet it’s these very circuits that create huge design challenges, and introduce a whole new class of verification problems that traditional approaches can’t begin to adequately address.

Fortunately there’s a group of companies bringing to market innovative solutions that focus exactly on these problems, and collaborating to hold the nanometer Circuit Verification Forum (nmCVF), on September 22[SUP]nd[/SUP] at TechMart in Santa Clara. Hosted by Berkeley Design Automation, and including technologists from selected EDA, industry and academic partners, this forum will showcase advanced nanometer circuit verification technologies and techniques. You’ll hear real circuit case studies, where these solutions have been used to verify challenging nanometer circuits, including data convertors; clock generation and recovery circuits (PLLs, DLLs); high-speed I/O, image sensors and RFCMOS ICs.

In addition to technical presentations and case studies, renowned EDA industry veteran and visionary, Jim Hogan, will give the keynote address.

Schedule
9:00- Registration
9:30- Welcome and Keynote
10:00- Morning sessions (including break)
12:30- Lunch
1:30- Afternoon sessions (including break)
4:30- Solution demonstrations and reception
6:30 - Forum wrap-up and close

Topic Areas
Application Examples
- Data converters
- PLLs and timing circuits
- High-Speed I/O
- Image sensors

Emerging Verification Technologies
- Nanometer device modeling
- Rapid prototyping including parasitic effects
- Thermal-aware circuit verification
- Variation-aware circuit design
- Circuit optimization and analysis

You should plan to attend if you’re a practicing circuit designer or a hands-on design manager, and you’re looking for high-integrity and comprehensive circuit verification solutions, focused on improving your circuit and getting it faster to market and faster to volume production.

Register HEREfor the nanometer Circuit Verification Forum, or see nm-forum.comfor more details. This event is FREE so you know I will be there!





[post_title] => Nanometer Circuit Verification Forum [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => nanometer-circuit-verification-forum [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:40:03 [post_modified_gmt] => 2019-06-15 02:40:03 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/nanometer-circuit-verification-forum.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 744 [post_author] => 28 [post_date] => 2011-08-28 16:00:00 [post_date_gmt] => 2011-08-28 16:00:00 [post_content] => Whether you use a gate-first or gate-last High-k Metal Gate implementation, yield will be your #1 concern at 28nm, which makes variation analysis and verification a big challenge. One of the consulting projects I have been working on with the foundries and top fabless semiconductor companies is High-Sigma Monte Carlo (HSMC) verification technologies. It has been a bumpy two years certainly, but the results make for a good blog so I expect this one will be well read.

GLOBALFOUNDRIES Selects Solido Variation Designer for High-SigmaMonte Carlo
and PVT Design in its AMS Reference Flow


“We are pleased to work with Solido to include variation analysis and design methodology in our AMS Reference Flow,” said Richard Trihy, director of design enablement, at GLOBALFOUNDRIES. “SolidoVariation Designer together with GLOBALFOUNDRIES models makes it possible to perform high-sigma design for high-yield applications.”

Solido HSMC is a fast, accurate, scalable, and verifiable technology that can be used both to improve feedback within the design loop, as well as for comprehensive verification of yield critical high-sigma designs.

Since billions of standard Monte Carlo (MC) simulations would be required for six sigma verification, most yield sensitive semiconductor designers use a small number of MC runs and extrapolate the results. Others manually construct analytical models relating process variation to performance and yield. Unfortunately, both approaches are time consuming and untrustworthy at 28nm HKMG.

Here are some of the results I have seen during recent evaluations and production use of Solido HSMC:

Speed:

  • 4,700,000x faster than Monte Carlo for 6-sigma analysis
  • 16,666,667x fewer simulations than Monte Carlo for 6-sigma analysis
  • Completed in approximately 1 day, well within production timelines

Accuracy:

  • Properly determined performance at 6-sigma, with an error probability of less than 1e-12
  • Used actual Monte Carlo samples to calculate results
  • Provided high-sigma corners to use for design debug

Scalable:

  • Scaled to 6-sigma (5 billion Monte Carlo samples)
  • Scaled to more than 50 process variables

Verifiable:

  • Error probability was reported by the tool
  • Results used actual Monte Carlo samples – not based on mathematical estimates


Mohamed Abu-Rahma of Qualcomm did a presentation at #48DAC last June in San Diego. A video of his presentation can be seen HERE. Mohamed used Solido HSMC and Synopsys HSPICE for six sigma memory design verification.

Other approaches to six-sigma simulation include:


  • Quasi Monte Carlo (QMC)
  • Direct Model-based
  • Worst-Case Distance (WCD)
  • Rejection Model-Based (Statistical Blockade)
  • Control Variate Model-Based (CV)
  • Markov Chain Monte Carlo (MCMC)
  • Importance Sampling (IS)

None of which were successful at 28nm due to excessive simulation times and the inability to correlate with silicon. Especially the Worst-Case Distance approach, which is currently being peddled by an EDA vendor who’s name I will not mention. They claim it correlates to silicon but it does not! Not even close! But I digress…..

Being from Virage Logic and working with Solido the last two years, this blog is based on my personal experience. If you have hard data that suggests otherwise let me know and I will post it.

I would love to describe in detail how Solido solved this very difficult problem. Unfortunately I’m under multiple NDA’s with the penalty of death and dismemberment (not necessarily in that order). You can download a Solido white paper on high-sigma Monte Carlo verification HERE. There is another Solido white paper that goes into greater detail of how they solved this problem but it requires an NDA. You can also get a Webex HSMC briefing by contacting Solido directly HERE. I observed one just last week and it was quite good, I highly recommend it!





 [post_title] => Semiconductor Yield @ 28nm HKMG! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => semiconductor-yield-28nm-hkmg [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:07 [post_modified_gmt] => 2019-06-15 01:53:07 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/semiconductor-yield-28nm-hkmg.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 755 [post_author] => 28 [post_date] => 2011-09-05 18:14:00 [post_date_gmt] => 2011-09-05 18:14:00 [post_content] => While I was in Taiwan last month battling a Super Typhoon, Morris Chang was in Silicon Valley picking up his IEEE Medal of Honor. Gordon Moore, Andrew Grove, and Robert Noyce all have medals. The other winners, including 10 Nobel prize recipients, are listed HERE. An updated wiki on Dr. Morris Chang is located HERE.

The 12+ hour plane ride home gives a person plenty of time for reflection on why TSMC is so successful. Leadership is certainly important, just take a look at the executive staff on the new TSMC corporate website ( www.tsmc.com ). But in my opinion, TSMC's success boils down to one thing, they are a dedicated IC foundry that is dependent on its customers and ecosystem partners and TSMC has never forgotten that.

Foundry 2010 Revenues:
(1) TSMC $13B
(2) UMC $4B
(3) GFI $3.5B
(4) SMIC $1.5B
(5) Dongbu $512M
(6) Tower/Jazz $509M
(7) Vanguard $508M
(8) IBM $430M
(9) Samsung $420M
(10) MagnaChip $405M


But if you ask how TSMC and Dr. Morris Chang himself got where they are today it can be summed up in three words: Business Model Innovation. Other business model innovators include: eSilicon, ARM, Apple, Dell, Starbucks, Ebay, Google, etc…. I would argue that without TSMC some of these businesses would not even exist.

Morris Chang’s education started at Harvard but quickly moved to MIT as his interest in technology began to drive his future. From MIT mechanical engineering graduate school Morris went directly into the semiconductor industry at the process level and was quickly moved to management. After completing an electrical engineering PhD program at Stanford, Morris leveraged his process level semiconductor management success and went to Taiwan to head the Industrial Technology Research Institute (ITRI) which lead to the founding of TSMC.

In 1987 TSMC started 2 process nodes behind current semiconductor manufacturers (IDMs). Morris Chang made the first TSMC sales calls with a single brochure: TSMC Core Values: Integrity, commitment, innovation, partnership. 4-5 years later TSMC was only behind 1 node and the orders started pouring in. In 10 years TSMC caught up with IDMs (not Intel) and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing.

Morris Chang Awards



  • 1998, "Top 25 Managers of the Year" and "Stars of Asia" by Business Week.
  • 1998, "One of The Most Significant Contributors in the 50 years of Semiconductor Industry" by BancAmerica Robertson Stephens.
  • 2000, "IEEE RobertN. Noyce Award" for Exceptional Contributions to Microelectronics Industry.
  • 2000, "Exemplary Leadership Award" from the Fabless Semiconductor Association (GSA).
  • 2005, "Top 10 Most Influential Leaders of the World" by Electronic Business.
  • 2008, "Semiconductor Industry Association's Robert N. Noyce Award"
  • 2009, "EE Times Annual Creativity in Electronics Lifetime Achievement Award"
  • 2011, IEEE Medal of Honor

Dr. Morris Chang turned 80 on July 10[SUP]th[/SUP] 2011, I have seen him in Fab 12 but we have not met. Morris returned to the CEO job in June of 2009 and is still running TSMC full time as CEO and Chairman. He works from 8:30am to 6:30pm like most TSMC employees and says that a successful company life cycle is: rapid expansion, a period of consolidation, and maturity. The same could be said about Morris himself.

Here is a new 5 minute video from TSMC. I highly recommend watching it:

Pioneer of Dedicated IC Foundry Business Model

Related Blogs:TSMC 28nm / 20nm Update!




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TSMC and Dr. Morris Chang!

TSMC and Dr. Morris Chang!
by Daniel Nenni on 09-05-2011 at 6:14 pm

While I was in Taiwan last month battling a Super Typhoon, Morris Chang was in Silicon Valley picking up his IEEE Medal of Honor. Gordon Moore, Andrew Grove, and Robert Noyce all have medals. The other winners, including 10 Nobel prize recipients, are listed HERE. An updated wiki on Dr. Morris Chang is located HERE.

The 12+ hour plane… Read More


Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics

Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics
by Daniel Payne on 09-05-2011 at 3:37 pm

Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented… Read More


What changes to expect in Verification IP landscape after Synopsys acquisition of nSys?

What changes to expect in Verification IP landscape after Synopsys acquisition of nSys?
by Eric Esteve on 09-05-2011 at 4:53 am

Even if nSys acquisition by Synopsys will not have a major impact on Synopsys’ balance sheet, it is a kind of earthquake in the Verification market landscape. After the Denali acquisition by Cadence in 2010, nSys was most probably the market leader in verification IP, if we look at the independent VIP providers (excluding Cadence).… Read More


HP Will Farm Out Server Business to Intel

HP Will Farm Out Server Business to Intel
by Ed McKernan on 09-04-2011 at 7:36 pm


In a Washington Post Column this past Sunday, Barry Ritholtz, A Wall St. Money Manager and who has a blog called the Big Picture, recounts the destruction that Apple has inflicted on a wide swath of technology companies (see And then there were none). He calls it “creative destruction writ large.” Ritholtz though is only accounting… Read More


I love you, you love me, we’re a happy family…

I love you, you love me, we’re a happy family…
by Paul McLellan on 08-31-2011 at 8:00 pm

The CEO panel at the 2nd GTC wasn’t especially enlightening. The theme was that going forward will require cooperation for success and everyone was really ready to cooperate.

The most interesting concept was Aart talking about moving from what he called “scale complexity” aka Moore’s law to what he … Read More


Global Technology Conference 2011

Global Technology Conference 2011
by Paul McLellan on 08-31-2011 at 7:07 pm

I went to the second Global Technology Conference yesterday. It started with a keynote by Ajit Manocha who is the CEO of about 2 months. I hadn’t realized until someone asked him during the press lunch that he is technically only the “acting” CEO. Actually, given his experience he might be the right person anyway,… Read More


Economic news not all bad for semiconductors

Economic news not all bad for semiconductors
by Bill Jewell on 08-30-2011 at 2:06 pm



The economic news lately has been bleak. U.S. GDP grew at an anemic 0.4% in 1Q 2011 and 1.0% in 2Q 2011 – leading to increased concerns about a double-dip recession. High government debt levels in the U.S. and several European nations have contributed to volatile stock markets. The news does not seem to be any better for the semiconductorRead More


Apple’s $399 Plan to Win Consumer Market in Summer 2012

Apple’s $399 Plan to Win Consumer Market in Summer 2012
by Ed McKernan on 08-30-2011 at 10:30 am

The complete destruction of the consumer PC market in the US and Europe is well within Apple’s grasp and will begin to unfold next summer. There is nothing that Intel, Microsoft or the retail channels can do to hold back the tsunami that was first set in motion with the iPad last year and comes to completion with the introduction of one… Read More


Nanometer Circuit Verification Forum

Nanometer Circuit Verification Forum
by Daniel Nenni on 08-29-2011 at 2:33 pm

Verifying circuits on advanced process nodes has always been difficult, and it’s no easier with today’s nanometer CMOS processes. There’s a great paradox in nanometer circuit design and verification. Designers achieve their greatest differentiation when they implement analog, mixed-signal, RF and custom … Read More


Semiconductor Yield @ 28nm HKMG!

Semiconductor Yield @ 28nm HKMG!
by Daniel Nenni on 08-28-2011 at 4:00 pm

Whether you use a gate-first or gate-last High-k Metal Gate implementation, yield will be your #1 concern at 28nm, which makes variation analysis and verification a big challenge. One of the consulting projects I have been working on with the foundries and top fabless semiconductor companies is High-Sigma Monte Carlo (HSMC) … Read More