Mentor Graphics Should Be Acquired or Sold: Carl Icahn

Mentor Graphics Should Be Acquired or Sold: Carl Icahn
by Daniel Nenni on 02-12-2011 at 5:42 pm

The big EDA news last week of course was the CNBC interview (HERE) with infamous corporate raider Carl Icahn. Carl is not happy with Mentor Executives, nor is Mentor investor Donald Drapkin who said, and I quote, “It’s just a sleepy company run like a country club”. Carl and Donald’s combined MENT investment is 20%+ … Read More


New ERC Tools Catch Design Errors

New ERC Tools Catch Design Errors
by glforte on 02-11-2011 at 2:18 pm

A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan

Today’s IC designs are complex. They contain vast arrays of features and functionality in Read More


EDA and Wall Street

EDA and Wall Street
by Paul McLellan on 02-11-2011 at 1:25 pm

Good news in a way: Merrill Lynch (or Bank of America Merrill Lynch as I suppose we have to get used to calling them) have re-started coverage of EDA with a 20 page report on the industry, much of which is spent on explaining how the industry segments out and who is strong in which segments, stuff that most people reading this site already… Read More


DRC+, DFM, CMP, Variablility

DRC+, DFM, CMP, Variablility
by Daniel Payne on 02-10-2011 at 12:42 pm

When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.

(United States Patent 6661699. Inventor:… Read More


Keynote Address at the 16th Asia and South Pacific Design Automation Conference

Keynote Address at the 16th Asia and South Pacific Design Automation Conference
by Daniel Nenni on 02-06-2011 at 6:23 pm

"Managing increasing complexity through higher-level of abstraction: What the past has taught us about the future" Dr. Ajoy Bose, Atrenta CEO

Here is the abstract:
Time to market and design complexity challenges are well-known; we have all seen the statistics and predictions. A well-defined strategy to address Read More


TSMC Raises The Semiconductor Bar With 450mm!

TSMC Raises The Semiconductor Bar With 450mm!
by Daniel Nenni on 02-03-2011 at 2:34 pm

During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!

According to Morris Chang:

“FRead More


DesignCon 2011 Trip Reports!

DesignCon 2011 Trip Reports!
by Daniel Payne on 02-01-2011 at 1:38 pm

Cadence at DesignCon 2011

I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.

Silicon Realization Trends and Challenges:

Silicon Realization – end to end digital… Read More


Semiconductor Quidditch @ DesignCon 2011!

Semiconductor Quidditch @ DesignCon 2011!
by Daniel Nenni on 01-26-2011 at 10:09 pm

Process Design Kit (PDK) development is one of the most entertaining things to watch in the semiconductor design world. It is kind of like the Golden Snitch in the game of Quidditch. No matter how rough EDA vendors play the game, no matter what the score is, it’s the vendor that “gets” the Golden PDK Snitch that wins the semiconductor… Read More


IP-SoC trip report (part II): system level mantra

IP-SoC trip report (part II): system level mantra
by Eric Esteve on 01-24-2011 at 4:45 am

“IP Innovation is moving from component level to system level”. This mantra was heard during the conference, from various speakers: during the keynote talk by Ganesh R. from Gartner and presentation “Integration-Optimized IP from Cadence” by Ranga Srinivasan, also during discussion around coffee (or a glass Read More


TSMC Versus The FabClub!

TSMC Versus The FabClub!
by Daniel Nenni on 01-23-2011 at 11:00 pm


The Common Platform Technology Forum last week was not well attended, less than half than the GlobalFoundries Conference. It was deja vu of previous CP forums but there were a couple of surprises to go with the disappointment. The lunch line was long, but fortunately I was escorted to the press lunch featuring VIP’s from Samsung,… Read More