The CEO Fireside Chats were my very favorite part of #52DAC. Dr. Walden Rhines, Lip-Bu Tan, and Dr. Aart de Geus are heroes of the EDA industry, absolutely. I saw all three Fireside Chats and the one word that I’m left with is INSPIRED! … Read More
DDR stands for Don’t Do (Just) RTL
In optimizing SoC design for performance, there is so much focus on how fast a CPU core is, or a GPU core, or peripherals, or even the efficiency of the chip-level interconnect. Most designers also understand selecting high performance memory at a cost sweet spot, and optimizing physical layout to clock it as fast as possible within… Read More
Apple Watch Design Revisit with a Wi-Fi Twist
Apple Watch is the world’s most celebrated gadget in 2015. At the same time, however, early product reviews highlight some issues about slow apps, less than impressive user experience, and short battery life.
Apple, the master of artful integration, has done well for its reputation of elite hardware and has been able to … Read More
New Tool Suite to Accelerate SoC Integration
Today, an SoC is seen in the context of an optimized assembly of IPs; it’s no more a single monolithic chip design. It’s very common to see an ARM processor IP along with an interconnect IP, a memory IP, and couple of buses and interfaces IP in an SoC. Although the SoC seems to be an integrated collection of IPs, it can be very complex and… Read More
High Level Synthesis. Are We There Yet?
High level synthesis (HLS) seems to have been part of the backdrop of design automation for so long that it seems to be one of those things that nobody notices any more. But it has also crept up on people and gone from interesting technology to keep an eye on to getting genuine adoption. The first commercial product in the space was behavioral… Read More
Further Delays for Intel 10nm?
Intel’s 10nm may be reliving the 14nm elongated delay issue-
Schedules & tool delivery may be pushed even deeper into 2016-
Meanwhile Samsung & TSMC press on-
Could Intel be embarrassed?
… Read More
I Don’t Know Much About Aart…
Actually, like anyone who has been in EDA for more than a decade or two (or three) I know quite a bit about Aart. But I still learned quite a bit about his views at the Fireside Chat at DAC where Ed Sperling talked to Aart for three-quarters of an hour.
Aart has a great talent at taking various small trends in the industry and aggregating … Read More
Eyes Meet Innovations at DAC
It gives me a very nice, somewhat nostalgic, feeling after attending the 52[SUP]nd[/SUP] DAC. There was a period during my final academic year in 1990 and my first job when I used to search through good technical papers in DAC proceedings and try implementing those concepts in my project work. In general, representation from ‘R&D… Read More
Design Data Management: An Analog IP Porting Case Study
IQ-Analog Corp. offers “off-the-shelf” data converter intellectual property (IP) for multiple foundries. The San Diego, California–based semiconductor design firm also provides analog front-end (AFE) technology that it tailors according to customer needs. And that’s where the dilemma begins.
IQ-Analog’s… Read More
Extending EUV Lithography
I have previously written about SPIE day 1 and 2 so I want to wrap up my coverage with some impressions from days 3 and 4. My single biggest take away from the conference is that EUV has made tremendous progress in the last 12 months. Last year the mood of the conference was in my opinion pessimistic with respect to EUV, this year the mood… Read More
5 Expectations for the Memory Markets in 2025