It may seem odd to look to the CIA for viewpoints in this area but in in many ways they are just as concerned as we are. After all, in aggregate, widespread identity theft and hacking both internally and by foreign nationals, theft, electronic ransom and other illicit acts are as much a threat to the security of the country as they are … Read More
Unlocking Efficiency and Performance with Simultaneous Multi-ThreadingAn Akeana hosted webinar on Simultaneous Multi-Threading (SMT)…Read More
DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDAAI was everywhere at DAC. Presentations, panel discussions,…Read More
Synopsys Webinar – Enabling Multi-Die Design with IntelAs we all know, the age of multi-die…Read More
Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA
Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.… Read More
EDAC Name Changing for ESDA, but what about IP ?
The EDA Consortium (EDAC) has changed name for Electronic Systems Design Alliance (ESD Alliance). That’s a good reminder that IC are developed (thanks to Design Automation) to be integrated into a System. A wide design ecosystem support system development, including embedded software, design intellectual property (IP), … Read More
Self-contained low power Wi-Fi IP for IoT apps
The emerging theme of fit-for-purpose IoT parts gained yet another perspective, this time with ARM and CEVA chiming in on a low-power Wi-Fi approach outlined in a new webinar. It was a rather unique event with an abbreviated 25-minute presentation and an extended 35-minute Q&A that added a lot of insight.… Read More
Wearables Mean Continuous Growth in the Internet of Things Ecosystem
The Internet of Things encompasses a wide range of connected services, technologies, and hardware devices. Yet, for consumers, it is the growing number of portable and wearable devices that will be their main interface with IOT tech. The wearable device market is rapidly evolving, especially when it comes to smart watches and… Read More
“Thinking Outside the Chip”
While pushing Moore’s Law’s boundaries in the world of 2D packaging, companies are starting to explore nontraditional approaches towards designing integrated circuit chips. 2D packaging is currently the most used method in designing chips in the industry, and while it leads in efficiency of power and performance, it lacks … Read More
EUV is coming but will we need it?
I have written multiple articles about this year’s SPIE Advanced Lithography Conference describing all of the progress EUV has made in the last year. Source power is improving, photoresists are getting faster, prototype pellicles are in testing, multiple sites around the world are exposing wafers by the thousands and more. … Read More
Making PLM Actually Work for for IC Design
The topic of Product Lifecycle Management (PLM) conjures up images of usage on airplanes, tanks and cars. That’s because it was developed decades ago to help make product development and delivery more efficient for big expensive manufactured products. It worked well for its intended markets by combining and managing all the … Read More
Multiple Facets of Cyber Security Workshop!
Security is one of the new categories we track and it is keeping SemiWiki very busy. Security in itself, as a result of the FBI vs Apple comedy routine, but also security across the EDA, IP, ARM, Mobile, IoT, and Automotive categories. … Read More
2.5D supply chain takes HBM over the wall
SoC designers have hit the memory wall head on. Although most SoCs address a relatively small memory capacity compared with PC and server chips, memory power consumption and bandwidth are struggling to keep up with processing and content expectations. A recent webinar looks at HBM as a possible solution.… Read More
Should Intel be Split in Half?