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WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices

WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices
by Daniel Nenni on 07-03-2025 at 10:00 am

Ceva webinar AI Arch SEMI 400X400 250625

Edge AI is rapidly transforming how intelligent solutions are designed, from smart home devices to autonomous vehicles, healthcare gadgets, and industrial IoT. Yet, architects, chip designers, and product managers frequently grapple with a common and daunting challenge: creating efficient, high-performance AI solutions… Read More


WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs

WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs
by Daniel Nenni on 07-03-2025 at 6:00 am

CAST Compression IP Webinar 400x400

In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More


ChipAgents Tackles Debug. This is Important

ChipAgents Tackles Debug. This is Important
by Bernard Murphy on 07-02-2025 at 6:00 am

ChipAgents concept min

Innovation is never ending in verification, for performance, coverage, connection to verification plans and other aspects of DV. But debug, accounting for 40% of the verification cycle, has remained stubbornly resistant to significant automation. Debug IDEs help to visualize but don’t address the core problem: given a failure,… Read More


Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis

Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis
by Kalar Rajendiran on 07-01-2025 at 10:00 am

Innovator3D IC Solution Suite

In a major announcement at the 2025 Design Automation Conference (DAC), Siemens EDA introduced a significant expansion to its electronic design automation (EDA) portfolio, aimed at transforming how engineers design, validate, and manage the complexity of next-generation three-dimensional integrated circuits (3D ICs).… Read More


CEO Interview with Faraj Aalaei of Cognichip

CEO Interview with Faraj Aalaei of Cognichip
by Daniel Nenni on 07-01-2025 at 8:00 am

Faraj (1)

Faraj Aalaei is a successful visionary entrepreneur with over 40 years of distinguished experience in communications and networking technologies. As a leading entrepreneur in Silicon Valley, Faraj was responsible for building and leading two semiconductor companies through IPOs as a founder and CEO.

Post acquisition of … Read More


Rethink Scoreboards to Supercharge AI-Era CPUs

Rethink Scoreboards to Supercharge AI-Era CPUs
by Admin on 07-01-2025 at 6:00 am

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By Dr. Thang Minh Tran, CEO/CTO Simplex Micro

Today’s AI accelerators—whether built for massive data centers or low-power edge devices—face a common set of challenges: deep pipelines, complex data dependencies, and the high cost of speculative execution. These same concerns have long been familiar in high-frequency microprocessor… Read More


CEO Interview with Dr. Noah Strucken of Ferric

CEO Interview with Dr. Noah Strucken of Ferric
by Daniel Nenni on 06-30-2025 at 10:00 am

Noah Sturcken headshot

Noah Sturcken is a Founder and CEO of Ferric with over 40 patents issued and 15 publications on Integrated Voltage Regulators. Noah leads Ferric with focus on business development, marketing and new technology development. Noah previously worked at AMD R&D Lab where he developed Integrated Voltage Regulator (IVR) technology.… Read More


Jitter: The Overlooked PDN Quality Metric

Jitter: The Overlooked PDN Quality Metric
by Admin on 06-30-2025 at 6:00 am

Figure 1 – Accumulated jitter

The most common way to evaluate a power distribution network is to look at its impedance over the effective frequency range. A lower impedance will produce less noise when transient current is demanded by the IC output buffers. However, this transient current needs to be provided at the same time for each transition or jitter will… Read More


Facing the Quantum Nature of EUV Lithography

Facing the Quantum Nature of EUV Lithography
by Fred Chen on 06-29-2025 at 8:00 am

Absorbed Photons Exposing EUV

The topics of stochastics and blur in EUV lithography has been examined by myself for quite some time now [1,2], but I am happy to see that others are pursuing this direction seriously as well [3]. As advanced node half-pitch dimensions approach 10 nm and smaller, the size of molecules in the resist become impossible to ignore for … Read More


Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo

Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo
by Daniel Nenni on 06-27-2025 at 10:00 am

Dan is joined by Andrea Gallo, CEO of RISC-V International, the non-profit home of the RISC-V instruction set architecture standard, related specifications, and stakeholder community. Prior to joining RISC-V International, Gallo worked in leadership roles at Linaro for over a decade. He built Linaro’s server engineering… Read More