I’ve written recently about the trend to move more technology to the edge, to mobile devices certainly but also to IoT edge nodes. This is based particularly on latency, communications access and power considerations. One example is the move of deep reasoning apps to the edge to handle local image and voice recognition which would… Read More
Intel's Commitment to Corporate Responsibility: Driving Innovation and SustainabilityIntroduction by Lip-BU Tan: I’m an engineer at…Read More
Cadence's Strategic Leap: Acquiring Hexagon's Design & Engineering BusinessIn a bold move that underscores the accelerating…Read More
TSMC 2025 Update: Riding the AI Wave Amid Global ExpansionWelcome to the second half of a very…Read More
Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC InnovationToday Alchip Technologies, a Taipei-based leader in high-performance…Read More
WEBINAR: Functional ECO Solution for Mixed-Signal ASIC DesignThis webinar, in partnership with Easy-Logic Technology, is…Read More
Joe Costello and Other Luminaries Keynote at DAC
The most charismatic EDA CEO that I have ever witnessed is Joe Costello, who formed Cadence by merging SDA (Solomon Design Automation) and ECAD (known for DRC with Dracula). You will be impressed with his Monday keynote at DACon June 19th, starting at 9:15AM. Joe has long since left the EDA world and is currently the CEO of a company… Read More
Recipes for Low Power Verification
Synopsys hosted a tutorial on verification for low power design at DVCon this year, including speakers from Samsung, Broadcom, Intel and Synopsys. Verification for low power is a complex and many-faceted topic so this was a very useful update. There is a vast abundance of information in the slides which I can’t hope to summarize… Read More
Tesla’s Cat in the Bag
Some day soon, maybe this year or next, Tesla Motors is going to let the cat out of the bag that its cars are not only connected but are also subject to remote control. Remote control isn’t the sort of feature that consumers look for in their personal transportation, so it isn’t likely to be something Tesla is going to bring… Read More
Succeeding with 56G SerDes, HBM2, 2.5D and FinFET
eSilicon presented their advanced ASIC design capabilities at a seminar last Wednesday evening. This event was closed to the press, bloggers and analysts, but I managed to get some details from a friend who attended. The event title was: “Advanced ASICs for the Cloud-Computing Era: Succeeding with 56G SerDes, HBM2, 2.5D and FinFET… Read More
What’s better than silicon-proven IP? Lab bench-proven!
The SoC industry depends upon the availability of validated IP. SoC designs require a huge investment, and assume the external IP that is licensed from outside parties satisfies all functional and electrical specifications. To support that requirement, IP providers typically pursue a strategy to demonstrate their designs… Read More
Aldec Swings for the Fences
In today’s fast-moving technology markets, companies who are prepared to step up to opportunity can break out of traditional bounds to become players in bigger and fast-growing markets. It looks to me like Aldec is putting itself on that path. They have announced an end-to-end hardware/software co-verification solution… Read More
TSMC Talks About 22nm, 12nm, and 7nm EUV!
The TSMC Symposium was jam-packed this year with both people and information. I had another 60 minutes of fame in the Solido booth where I signed 100 books, thank you to all who stopped by for a free book and a SemiWiki pen. SemiWiki bloggers Tom Dillinger and Tom Simon were also there so look for more TSMC Symposium blogs coming in the… Read More
Six Reasons to Consider Using FPGA Prototyping for ASIC Designs
There’s no doubt that programmable logic in FPGAs have transformed our electronics industry for the better. If you do ASIC designs then there’s always the pressure of getting first silicon correct, with no functional or timing bugs, because bugs will cause expensive re-spins and delay time to market. ASIC designers… Read More
Webinar: CEVA on basestation design for 5G NR
Conventional wisdom is that 5G is still somewhere on the hype curve – expected to arrive someday but still not a near-term technology. As is often the case, conventional wisdom seems to be wrong. Coming out of this year’s Mobile World Congress in Barcelona, semiconductor and carrier heavyweights have committed to accelerate deployment… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet