When I had to define the various IP categories (processor, analog & mixed-signal, wired interfaces, etc.) to build the Design IP Report, I scratched my head for a while about the processor main category: how to define the sub-categories? Not that long ago, it was easy to identify a CPU IP core and a DSP IP core. As of today, if a DSP… Read More


AIM Photonics Catching Its Stride as They Move into 2nd Year
AIM Photonics held its 2017 Proposers Meetings on May 24[SUP]th[/SUP] in Rochester, NY. The meetings included a review of AIM’s progress and strategic direction by their TRB (technical review board) and a session targeted at PIC (photonic integrated circuit) design for multi-project wafer (MPW) runs. While these discussions… Read More
TCAD for TFT, LCD and OLED Displays
As I write there are multiple displays in front of me that use TFT, LCD or OLED displays:
- ViewSonic Monitors with 24″ display
- MacBook Pro with 15″ display
- iPad Air
- Samsung Galaxy Note 4
- Nexus 7 tablet
- Garmin Edge 820
Getting to IP Functional Signoff
In the early days of IP reuse and platform-based design there was a widely-shared vision of in-house IP development teams churning out libraries of reusable IP, which could then be leveraged in many different SoC applications. This vision was enthusiastically pursued for a while; this is what drove reusability standards and … Read More
Embedded FPGA IP update — 2nd generation architecture, TSMC 16FFC, and a growing customer base
Regular Semiwiki readers are aware that embedded FPGA (eFPGA) IP development is a rapidly growing (and evolving) technical area. The applications for customizable and upgradeable logic in the field are many and diverse — as a result, improved performance, greater configurable logic capacity/density, and comprehensive… Read More
RTL Correct by Construction
Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc)… Read More
PDA will exhibit at the 54th DAC
Platform Design Automation, Inc will exhibit at the 54th Design Automation Conference(DAC) on June 18-21 in Austin Convention Center, Texas, USA, in Booth #1929. What to Expect:… Read More
Consolidation and Design Data Management
Consensia, a Dassault Systemès channel partner, recently hosted a webinar on DesignSync, a long-standing pillar of many industry design flows (count ARM, Qualcomm, Cavium and NXP among their users). A motivation for this webinar was the impact semiconductor consolidation has had on the complexity of design data management,… Read More
Understanding Sources of Clock Jitter Critical for SOC’s
Jitter issues in SOC’s reside at the crossroads of analog and digital design. Digital designers would prefer to live in a world of clocks that are free from jitter effects. At the same time, analog designers can build PLL’s that are precise and finely tuned. However, when a perfectly working PLL is inserted into an SOC, things can … Read More
CEO Interview: Stanley Hyduke, founder and CEO of Aldec
Dr. Stanley Hyduke, founder and CEO of Aldec talks about how keeping pace with the evolution of FPGAs and listening to customers underpin the company’s success.… Read More
Intel’s Pearl Harbor Moment