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Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
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Adding Expertise to GenAI: An Insightful Study on Fine-TuningI wrote earlier about how deep expertise, say…Read More
It’s the summer of 2018, the summer of Fortnite, and we all know we are addicted. Addicted to email, Snapchat, Instagram, Fortnite, Facebook. We swap outdoor time on the trail for indoor time around the console. Our kids log into Snapchat every day on vacation to keep their streaks alive and then get lost in the stream.
We move less … Read More
There’s an old maxim that you can only improve what you measure, so quality experts have been talking about this concept for decades and our semiconductor industry has been the recipient of such practices to such an extent that we can now buy consumer products that include chips with over 5 billion transistors in them. You’ve… Read More
Among the companies that bought a license from AT&T to produce the transistor was Sony. While the U.S. maintained its lead in technology, other countries like Japan emerged as competitors. Semiconductor manufacturing was both labor intensive… Read More
The author of this article, Dündar Dumlugöl, is CEO of Magwel. He has 25 years of experience in EDA managing the development of leading products used for circuit simulation and high-level system design.
Every designer knows how tedious it can be to shuttle back and forth between their layout tool and analysis tools. Every time an… Read More
A root of trust, particularly a hardware root of trust, has become a central principle in well-architected design for security. The idea is that higher layers in the stack, from drivers and OS up to applications and the network, must trust lower layers. What does it help it to build great security into a layer if it can be undermined… Read More
Standard cell library developers are faced with a daunting task when it is time to create a library for a new process node. Porting an existing library can be a big help, but even then, manual modifications to 800 or more cells is still required. Each of those cells has many geometric elements are that affected by new design rules. All… Read More
In the semiconductor world we have divided our engineering talent up into many adjacent disciplines and each comes with their own job titles: Design engineers, Verification engineers, DFT engineers, Test engineers. When first silicon becomes available then everyone on the team, and especially management all have a few big … Read More
Switching translates to power. Similar to the recent slow down experienced by Moore’s Law, the constant power density (power demand per unit chip area) prescribed by Dennard scaling was no longer affordable across the technological scaling. While the contribution of leakage power component in advanced process nodes was getting… Read More
I’m on a mini-roll on the subject of high-level design for ML-based systems. No complaints from me, this is one of my favorite domains and is certainly a hot area; it’s great to that EDA vendors are so active in advancing ML-based design. Here I want to talk about the Catapult HLS flow for use in ML design.
Since I’ve covered the ML topic… Read More
A large part of the effort in designing SOCs has shifted to the integration of their constituent IP blocks. Many IP blocks used in SOCs come as ready to use components and the real work has become making them work together. Network on Chip (NoC) has been a huge help in this task, handling the interconnections between blocks and planning… Read More
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AI RTL Generation versus AI RTL Verification