WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
Silicon Catalyst on the Road to $1 Trillion IndustryThere were quite a few announcements at the…Read More
Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
CDC Verification for Safety-Critical Designs – What You Need to KnowVerification is always a top priority for any…Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read More
An update is now available here: Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV
The 5nm foundry (e.g., TSMC) node may see the introduction of 6-track cells (two double-width rails plus four minimum-width dense lines) with a minimum metal pitch in the neighborhood of 30 nm. IMEC had studied a representative… Read More
The Zero Trust Model of information #security simplifies how #information security is conceptualized by assuming there are no longer “trusted” interfaces, applications, traffic, networks, or users. It takes the old model— “trust but verify”—and inverts it, because recent breaches have proven that when an organization trusts,… Read More
Time to Change our Thinking:
It is time to work the other side of the communications equation. Send less data. But apply new synthetic data science and machine learning to get more and richer information: a way that requires the transfer of radically fewer actual bits – perhaps 1 or 2% of the bits – but with higher model fidelity.… Read More
We always warn clients that even in the best of times, Joint Ventures (JVs) in China always end in tears. And we are far from the best of times right now. There is a major example of this playing out right now with Arm China.
Arm’s China JV is, to put it simply, a bit of a mess. The Board has fired the CEO, but he has refused to leave. And owing… Read More
There is an interesting white paper out from Mentor on how a customer used the Solido Varation Designer tool to reduce Monte Carlo simulations. As you may know I worked for Solido for 10+ years up until they were acquired by Mentor in December of 2017. It was an incredible personal and professional experience. I have the highest respect… Read More
The COVID-19 pandemic has turned the business of reporting news into a funhouse mirror where reality is distorted, up is down, and hopes for improving health and marketplace conditions are simultaneously raised and dashed on a daily basis. The latest news-driven whiplash moment arrived this morning care of the Detroit Free Press
In this, the second part of a two-part series we delve further into defining worst case, this time focusing specifically on device performance.
In the last blog we talked about the steady increase in power density per unit silicon area and how worst case is definitely getting worse. We discussed how in each new FinFET node the dynamic… Read More
Want fast debug? Synopsys recently hosted a Webinar to show off the latest and greatest improvements to Verdi® in performance, memory demand and multi-tasking, among other areas.
Performance improvements
Taruna Reddy (PMM) and Allen Hsieh (Staff apps) presented features of the latest version, released in March – Taruna started… Read More
Turkey may be the first customer for the Kargu series of weaponized suicide drones specifically developed for military use. These semi-autonomous devices have been in development since 2017 and will eventually be upgraded to operate collectively as an autonomous swarm to conduct mass synchronized attacks.
This situation… Read More
Summary
A recent process enhancement in advanced nodes is to support the fabrication of contacts directly on the active gate area of a device. At the recent VLSI 2020 Symposium, the critical advantages of this capability were highlighted, specifically in the context of the behavior of RF CMOS devices needed for 5G designs.
Introduction… Read More
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