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Project-Centric Design Process, or IP-centric

Project-Centric Design Process, or IP-centric
by Daniel Payne on 04-14-2020 at 10:00 am

projects

How do most IC design teams organize their work during the design process?

Most design teams would say that they organize their work into a project-centric view, and that at the beginning of the process use a tool for requirements management, maybe a bug tracker, or some design management tool. On the four IC designs that I worked … Read More


Innovation in Verification April 2020

Innovation in Verification April 2020
by Bernard Murphy on 04-14-2020 at 6:00 am

Innovation

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea.

We’re getting a lot of hits on these blogs but would like really like to get feedback also.

The Innovation

Our next pick… Read More


Linley Spring Processor Conference Kicks Off – Virtually

Linley Spring Processor Conference Kicks Off – Virtually
by Mike Gianfagna on 04-13-2020 at 10:00 am

Linley Gwennap

The popular Linley Processor Conference kicked off its spring event at 9AM Pacific on Monday, April 6, 2020. The event began with a keynote from Linley Gwennap, principal analyst and president at The Linley Group. Linley’s presentation provided a great overview of the application of AI across several markets. Almost all of the… Read More


Webinar on Transient Simulation of Power Transistors in Converter Circuits

Webinar on Transient Simulation of Power Transistors in Converter Circuits
by Tom Simon on 04-13-2020 at 6:00 am

PTM TR high side low side currents 300x182 1

Magwel is offering a webinar that takes a deeper look at how Power Transistors can be more accurately simulated in converter circuits to provide extremely accurate information about switching efficiency. DC converter circuit efficiency has a big effect on the battery life of mobile devices and can affect performance and efficiency… Read More


Online Class: Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)

Online Class: Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)
by Daniel Nenni on 04-12-2020 at 9:00 am

3D Finet Model

Our friends at Threshold Systems have a new ONLINE class that may be of interest to you. It’s an updated version of the Advanced CMOS Technology class held last February. This is normally a classroom affair but to accommodate the recent COVID-19 travel restrictions it is being offered virtually.

As part of the previous class we did… Read More


SiFive in a Virtual World Webinar Series 2020

SiFive in a Virtual World Webinar Series 2020
by Swamy Irrinki on 04-10-2020 at 6:00 pm

Rapid Embedded Prototyping with SiFive Software

Introducing the SiFive Connect Webinar Series –A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions

After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached… Read More


Wally Rhines: Mentoring Generations of Semiconductor and EDA Professionals

Wally Rhines: Mentoring Generations of Semiconductor and EDA Professionals
by Mike Gianfagna on 04-10-2020 at 10:00 am

Wally Then and Now

I had the good fortune to catch a live webinar recently that was quite compelling – Conversation with Dr. Walden Rhines: Predicting Semiconductor Business Trends After Moore’s Law! Dr. Rhines, known to most as Wally, doesn’t need much of an introduction. Any semiconductor or EDA professional knows who he is and what he’s accomplished.… Read More


Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs

Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs
by Herb Reiter on 04-10-2020 at 6:00 am

2d 3d Semiconductor Packaging SemiWiki Cadence

I had the opportunity to preview the upcoming SemiWiki webinar titled: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs. John Park’s message, describing this powerful Cadence solution, really impressed me. That’s why I want to encourage you to register for it and join this SemiWiki … Read More


Why I’m Lowering Semiconductor Equipment Revenue Growth to -6.9% in 2020

Why I’m Lowering Semiconductor Equipment Revenue Growth to -6.9% in 2020
by Robert Castellano on 04-09-2020 at 10:00 am

Applied Materials Lam lower C2

Because of significant $4 billion in equipment pull-ins in Q4 from sales in Asia, I was reducing my semiconductor wafer front-end (WFE) equipment revenue growth from an earlier +5% to 0% in 2020. Now, based on CORVID-19, I am further reducing revenue growth to -6.9%.

Chart 1 also shows the cyclical nature of semiconductors and semiconductor… Read More


Learning to Live with the Gaps Between Design and Verification

Learning to Live with the Gaps Between Design and Verification
by Tom Simon on 04-09-2020 at 6:00 am

Learning to live with the gaps between design and verification

Whenever I am asked to explain how chip design works by someone who is unfamiliar with the process, I struggle to explain the different steps in the flow. It also makes me aware of the discrete separations between each phase of activities. Of course, when you speak to a novice it is not even possible to get more than one layer down in the… Read More