The number of touchpoints between analog and digital circuits in high performance SoCs is increasing. This is not a problem because it is possible to implement critical analog blocks directly on nanometer scale digital ICs. However, in many cases digital interfaces or digital feedback circuitry configures these analog blocks… Read More





CEO Interview: Anna Fontanelli of Monozukuri
Anna has more than 25 years of expertise in managing complex R&D organizations and programs, giving birth to a number of innovative EDA technologies. She has pioneered the study and development of several generations of IC and package co-design environments and has held senior positions at leading semiconductor and EDA … Read More
The Big Three Weigh in on Emulation Best Practices
As software content increases in system-on-chip and system-in-package designs, emulation has become a critical enabling technology for the software team. This technology offers software developers the opportunity to verify their code in against a high-fidelity model of the target system that actually executes fast enough… Read More
Interconnect Basics: Wires to Crossbar to NoC
To many of us, if we ever think about interconnect on an SoC, we may think delay, power consumption, congestion, that sort of thing. All important points from an implementation point of view, but what about the functional and system implications? In the early days, interconnect was very democratic, all wires more or less equal, … Read More
SEMICON West – Applied Materials Selective Gap Fill Announcement
At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.… Read More
A “Super” Technology Mid-life Kicker for Intel
Summary
At the recent Intel Architecture Day 2020 symposium, a number of technology enhancements to the Intel 10nm process node were introduced. The cumulative effect of these enhancements would provide designs with a performance boost (at iso-power) approaching 20% – a significant intra-node enhancement, to be sure. The… Read More
Intel 10nm SuperFin Technology!
I made it through the Virtual Intel Architecture Day last week and much to my surprise it was very well done. Virtual events have been hit and miss but this one was definitely a hit. Great content, approachable experts, a glitch-free experience. The mainstream media has been redundantly covering it so let me add my many years of experience,… Read More
AMAT- Solid QTR & Great Guide- Share gains- Memory?
Higher Foundry/logic exposure helps-
Little or no Covid or China trade impact-
Nice quarter but even better guide-
Applied reported revenues of $4.4B and NonGAAP EPS of $1.06, nicely above street estimates of $4.2B and $0.95 in EPS. Guidance is for revenues $4.6B +-$200M and EPS of $1.17+- $0.06, versus current expectations of… Read More
Uber: Dara’s Distracted Driving
Uber has taken a highly profitable business and turned it into a very unprofitable and dangerous one with the help of the pandemic. With guile, innovation, and theft, Uber founder and pitchman, Travis Kalanick, spun up the ride hailing wonder into a global transportation leader built upon rapid growth and a bare knuckle approach… Read More
NetApp: Comprehensive Support for Moving Your EDA Flow to the Cloud
With this post, we welcome NetApp to the SemiWiki family. NetApp was founded in 1992 with a focus on data storage solutions. Initial market segments were high-performance computing (HPC) and EDA and their first customers were EDA and semiconductor companies. NetApp has become a primary force in on-premise data management for… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet