Tuesday at DAC was actually my very first time attending a technical session, and the presentation from Nebabie Kebebew, Siemens EDA, was called, Mitigating Variability Challenges of IPs for Robust Designs. There were three presentations scheduled for that particular Designer, IP and Embedded Systems track, but with the COVID… Read More
Revolutionizing Hardware Design Debugging with Time Travel TechnologyIn the semiconductor industry High-Level Synthesis (HLS) and…Read More
Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic TestingSilent Data Corruption (SDC) represents a critical challenge…Read More
TSMC's 6th ESG AWARD Receives over 5,800 Proposals, Igniting Sustainability PassionTaiwan Semiconductor Manufacturing Company has once again demonstrated…Read More
Tiling Support in SiFive's AI/ML Software Stack for RISC-V Vector-Matrix ExtensionAt the 2025 RISC-V Summit North America, Min…Read More
TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!Socionext’s recent run of rapid 3D-IC tape-outs is…Read More5 Talks on RISC-V
Veriest recently hosted a webinar focusing on RISC-V as a forerunner of ongoing open-source revolution in chip design. Speakers were distinguished professionals from industry and academia. Webinar covered topics from market trends to open-source hardware initiatives, tools and methodologies.
Zvonimir Bandić: RISC-V … Read More
Podcast EP54: Ventana Micro, RISC-V, HPC and Chiplets
Dan is joined by Balaji Baktha, founder and CEO of Ventana Micro. Balaji explores the application of RISC-V in high-performance applications and the specific advantages of a chiplet-based approach.
RISC-V Summit Panel: https://www.youtube.com/watch?v=duZaAhWxhWM
The views, thoughts, and opinions expressed in these… Read More
AI for EDA for AI
I’ve been noticing over the last few years that electronic design automation (EDA) vendors just love to talk about artificial intelligence (AI) and machine learning (ML), sometimes with deep learning (DL) and neural networks tossed in as well. It can get a bit confusing since these terms are used in two distinct contexts. The first… Read More
Scalable Concolic Testing. Innovation in Verification
Combining simulation and symbolic methods is an attractive way to excite rare branches in block-level verification, but is this method really scalable? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always,… Read More
Cut Out the Cutouts
In 2014, many of the customers that my team and I supported in North America were still using HFSS 3D to model boards and packages. These customers were content with that interface, able to get their models setup quickly, and were okay with the solution times because when HFSS gave them an answer, they knew it was the right answer. I … Read More
More Than Moore and Charting the Path Beyond 3nm
The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More
DAC 2021 – Siemens EDA talks about using the Cloud
My third event at DAC on Monday was all about using EDA tools in the Cloud, and so I listened to Craig Johnson, VP EDA Cloud Solutions, Siemens EDA. Early in the day I heard from Joe Sawicki, Siemens EDA, on the topic of Digitalization.
Why even use the Cloud for EDA? That’s a fair question to ask, and Craig had several high-level… Read More
Topics for Innovation in Verification
Paul, Raúl and I are having fun with our Innovation in Verification series, and you seem to be also, judging by the hit rates we’re getting. We track these carefully to judge what you find most interesting and what seems to fall more under the category of “Meh”. Paul and others also get informal feedback in client meetings but it would… Read More
DAC 2021 Wrap-up – S2C turns more than a few heads
Now that the 58th Design Automation Conference held this year in San Francisco has concluded, we take a minute to look back at the results and ascertain what it meant for our company.
Unfortunately, many popular tradeshows held in the time of Covid have suffered a drop in attendance, and DAC was no exception. Despite this however,… Read More


Quantum Advantage is About the Algorithm, not the Computer