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Podcast EP106: SoC Verification Flows and Methodologies with Sivakumar P R of Maven Silicon

Podcast EP106: SoC Verification Flows and Methodologies with Sivakumar P R of Maven Silicon
by Daniel Nenni on 09-14-2022 at 10:00 am
Categories: Uncategorized
1 Comment

Dan is joined by Sivakumar P R, the Founder and CEO of Maven Silicon. He is responsible for the company’s vision, overall strategy, business, and technology. He is also the Founder and CEO of ASIC Design Technologies.

Dan and Sivakumar discuss SoC Verification Flows and Methodologies based on his article published on SemiWiki.… Read More

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Machine Learning in the Fab at #59DAC

Machine Learning in the Fab at #59DAC
by Daniel Payne on 09-14-2022 at 8:00 am
Categories: EDA, Siemens EDA

Virtual Metrology min

It used to be true that a foundry or fab would create a set of DRC files, provide them to designers, and then the process yield would be acceptable, however if the foundry knows more details about the physical implementation of IC designs then they can improve the yield. Using a digital twin of the design, process and metrology steps… Read More

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Ultra-efficient heterogeneous SoCs for Level 5 self-driving

Ultra-efficient heterogeneous SoCs for Level 5 self-driving
by Don Dingee on 09-14-2022 at 6:00 am
Categories: AI, Automotive, Expedera, IP

Ultra-efficient heterogeneous SoCs target the AI processing pipeline for Level 5 self-driving

The latest advanced driver-assistance systems (ADAS) like Mercedes’ Drive Pilot and Tesla’s FSD perform SAE Level 3 self-driving, with the driver ready to take back control if the vehicle calls for it. Reaching Level 5 – full, unconditional autonomy – means facing a new class of challenges unsolvable with existing technology… Read More

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WEBINAR: Scalable, On-Demand (by the Minute) Verification to Reach Coverage Closure

WEBINAR: Scalable, On-Demand (by the Minute) Verification to Reach Coverage Closure
by Synopsys on 09-13-2022 at 10:00 am
Categories: EDA, Events, Synopsys

Synopsys Verification Cloud Solutions

Verification has long been the most time-consuming and often resource-intensive part of chip development. Building out the infrastructure to tackle verification can be a costly endeavor, however. Emerging and even well-established semiconductor companies must weigh the Cost-of-Results (COR) against Time-to-Results

… Read More
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Connecting SystemC to SystemVerilog

Connecting SystemC to SystemVerilog
by Bernard Murphy on 09-13-2022 at 6:00 am
Categories: EDA, Siemens EDA

UVM Connect

Siemens EDA is clearly on a mission to help verifiers get more out of their tools and methodologies. Recently they published a white paper on UVM polymorphism. Now they have followed with a paper on using UVM Connect, re-introducing how to connect between SystemC and SystemVerilog. I’m often mystified by seemingly overlapping… Read More

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Truechip: Customer Shipment of CXL3 VIP and CXL Switch Model

Truechip: Customer Shipment of CXL3 VIP and CXL Switch Model
by Kalar Rajendiran on 09-12-2022 at 10:00 am
Categories: IP, Truechip

CXL Block Diagram

The tremendous amount of data generated by AI/ML driven applications and other hyperscale computing applications have forced the age old server architecture to change. The new architecture is driven by the resource disaggregation paradigm, wherein memory and storage are decoupled from the host CPU and managed independently… Read More

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WEBINAR: Unlock your Chips’ Full Data Transfer Potential with Interlaken

WEBINAR: Unlock your Chips’ Full Data Transfer Potential with Interlaken
by Daniel Nenni on 09-12-2022 at 6:00 am
Categories: Comcores, Events, IP

Interlaken Blog Post Graphic

Way back in the early 2000s when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s … Read More

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GM Buyouts: Let’s Get Small!

GM Buyouts: Let’s Get Small!
by Roger C. Lanctot on 09-11-2022 at 6:00 am
Categories: Automotive
7 Comments

GM Buyouts Lets Get Small

“I sell new cars to legitimize my used car business.”  – Wes Lutz, president Extreme Chrysler/Dodge/Jeep, RAM Inc., Jackson, Mich. National Automobile Dealer Association board member

Since taking over at General Motors, CEO Mary Barra has made many radical adjustments in the company’s international footing in the interest… Read More

Podcast: Intel’s RISC-V Ecosystem initiative with Junko Yoshida

Podcast: Intel’s RISC-V Ecosystem initiative with Junko Yoshida
by Daniel Nenni on 09-09-2022 at 10:00 am
Categories: Uncategorized

Welcome to our Podcast on Intel’s RISC-V Ecosystem initiative. I’m Junko Yoshida, Editor in Chief‌ of the Ojo-Yoshida Report. Joining me today to discuss the topic are Vijay Krishnan, general manager of RISC-V Ventures at Intel Corp. and Emerson Hsiao, chief operating officer of Andes Technologies USA

The views,… Read More

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CEO Interview: Jan Peter Berns from Hyperstone

CEO Interview: Jan Peter Berns from Hyperstone
by Daniel Nenni on 09-09-2022 at 6:00 am
Categories: CEO Interviews, Hyperstone GmbH, IP
2 Comments

DSCF07001

Since 2012, Dr. Jan Peter Berns is the CEO of Hyperstone, a producer of Flash Memory Controllers for Industrially Embedded Storage Solutions. Before that, he held a Senior Manager Position at Toshiba Electronics for several years. Jan Peter brings more than 20 years of management and executive experience in the semiconductor… Read More